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lecture 3 - ARM Architecture Overview EEC 170 32-bit RISC...

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1 EEC 170 ARM Architecture ARM Architecture Overview 32-bit RISC Load-Store architecture Focus: power, code size, performance More complex that MIPS, much smaller code size Much less complex than x86, a bit larger code size Different variations target different markets Performance (e.g., Smartphones, Tablets) : Cortex-A9 2GHz, multi-core, 8 stage O-O-O pipeline, three-issue Real-time (e.g., Automotive): Cortex-R4 400Mhz, 8 stage pipeline, two-issue, optional FPU, ECC Microcontroller: Cortex-M3 50Mhz, 3 stage pipeline, single issue, no cache ARM Registers 16 registers: R 0 -R 15 13 general-purpose registers: R 0 -R 15 R 0 not hardwired to zero like MIPS R 13 : Stack pointer, by software convention R 14 : Link register, like MIPS R 15 : Program counter Addressing Modes ARM has many addressing modes vs. MIPS’ one + Reduces code size and power - Increases hardware complexity, may increase clock cycle time Basic mode: Immediate Offset (only mode in MIPS): LDR R d ,[R base ,#] ; Effective Address (EA) = (R base ) + # ; # is12-bit two’s-complement immediate
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2 Addressing Modes Immediate Post Indexed ; Auto increment LDR R d ,[R base ],# ; EA = (R base ) + # ; R base = R base + # ; useful for striding through arrays Register Offset LDR R d ,[R base ,R offset ] ; EA = (R base ) + (R offset ) ; useful for accessing arbitrary offset ; into data structure, relative to the start strcpy LDRB R2,[R1],#1 STRB R2,[R0],#1 TST R2,R2 ; repeat if R2 !=0
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