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74HC_HCT00_3 - INTEGRATED CIRCUITS DATA SHEET 74HC00...

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DATA SHEET Product specification Supersedes data of 1997 Aug 26 2003 Jun 30 INTEGRATED CIRCUITS 74HC00; 74HCT00 Quad 2-input NAND gate
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2003 Jun 30 2 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 FEATURES Complies with JEDEC standard no. 8-1A ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Specified from - 40 to +85 ° C and - 40 to +125 ° C. DESCRIPTION The 74HC00/74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC00/74HCT00 provide the 2-input NAND function. QUICK REFERENCE DATA GND = 0 V; T amb = 25 ° C; t r = t f = 6 ns. Notes 1. C PD is used to determine the dynamic power dissipation (P D in μ W). P D = C PD × V CC 2 × f i × N + Σ (C L × V CC 2 × f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pF; V CC = supply voltage in Volts; N = total load switching outputs; Σ (C L × V CC 2 × f o ) = sum of the outputs. 2. For 74HC00 the condition is V I = GND to V CC . For 74HCT00 the condition is V I = GND to V CC - 1.5 V. FUNCTION TABLE See note 1. Note 1. H = HIGH voltage level; L = LOW voltage level. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT 74HC00 74HCT00 t PHL /t PLH propagation delay nA, nB to nY C L = 15 pF; V CC = 5 V 7 10 ns C I input capacitance 3.5 3.5 pF C PD power dissipation capacitance per gate notes 1 and 2 22 22 pF INPUT OUTPUT nA nB nY L L H L H H H L H H H L
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2003 Jun 30 3 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 ORDERING INFORMATION TYPE NUMBER PACKAGE TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE 74HC00N - 40 to +125 ° C 14 DIP14 plastic SOT27-1 74HCT00N - 40 to +125 ° C 14 DIP14 plastic SOT27-1 74HC00D - 40 to +125 ° C 14 SO14 plastic SOT108-1 74HCT00D - 40 to +125 ° C 14 SO14 plastic SOT108-1 74HC00DB - 40 to +125 ° C 14 SSOP14 plastic SOT337-1 74HCT00DB - 40 to +125 ° C 14 SSOP14 plastic SOT337-1 74HC00PW - 40 to +125 ° C 14 TSSOP14 plastic SOT402-1 74HCT00PW - 40 to +125 ° C 14 TSSOP14 plastic SOT402-1 74HC00BQ - 40 to +125 ° C 14 DHVQFN14 plastic SOT762-1 74HCT00BQ - 40 to +125 ° C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1A data input 2 1B data input 3 1Y data output 4 2A data input 5 2B data input 6 2Y data output 7 GND ground (0 V) 8 3Y data output 9 3A data input 10 3B data input 11 4Y data output 12 4A data input 13 4B data input 14 V CC supply voltage Fig.1 Pin configuration DIP14, SO14 and (T)SSOP14. handbook, halfpage 00 MNA210 1 2 3 4 5 6 7 1A 1B 1Y 2A 2B 2Y GND V CC 4B 4A 4Y 3B 3A 3Y 14 13 12 11 10 9 8
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2003 Jun 30 4 Philips Semiconductors Product specification Quad 2-input NAND gate 74HC00; 74HCT00 Fig.2 Pin configuration DHVQFN14. handbook, halfpage 1 14 1A V CC 7 2 3 4 5 6 1B 1Y 2A 2B 2Y 13 12 11 10 9 4B 4A 4Y 3B 3A 8 GND 3Y MNA950 GND (1) Top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
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