lpm - LPM Quick Reference Guide December 1996 ® About this...

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Unformatted text preview: LPM Quick Reference Guide December 1996 ® About this Quick Reference Guide December 1996 The LPM Quick Reference Guide provides information on functions in the library of parameterized modules (LPM) and on custom parameterized functions created by Altera®. How to Contact Altera For additional information about Altera products, consult the sources shown in Table 1. Table 1. How to Contact Altera Information Type Literature Access Altera Express USA & Canada (800) 5-ALTERA All Other Locations (408) 894-7850 Altera Literature Services (888) 3-ALTERA, Note (1) (888) 3-ALTERA; [email protected], Note (1) Non-technical customer service Technical support Telephone hotline Fax Telephone hotline (8:00 a.m. to 5 p.m. Pacific Time) Fax Bulletin board service Electronic mail FTP site CompuServe General product information Note: (1) You can also contact your local Altera sales office or sales representative. See “Altera Sales Offices” in this quick reference guide. (800) SOS-EPLD (408) 954-8186 (800) 800-EPLD (408) 894-7000 (408) 954-8186 (408) 894-7000, Note (1) (408) 954-0348 (408) 954-0104 [email protected] ftp.altera.com go altera (408) 894-7104 http://www.altera.com (408) 954-0348, Note (1) (408) 954-0104 [email protected] ftp.altera.com go altera (408) 894-7104, Note (1) http://www.altera.com Telephone World-wide web Altera Corporation iii About this Quick Reference Guide Typographic Conventions This LPM Quick Reference Guide uses the typographic conventions shown in Table 2. Table 2. LPM Quick Reference Guide Conventions Visual Cue Bold italics “Subheading Title” Courier font Meaning Book titles are shown in bold italics, with initial capital letters. Example: LPM Quick Reference Guide Subheadings within a quick reference guide section and titles of MAX+PLUS II Help topics are shown in quotation marks. Example: “Altera Sales Offices” Function names and port names are shown in lowercase Courier. For example: lpm_and, data Parameter names are shown in uppercase Courier. For example: LPM_WIDTH, LPM_DIRECTION iv Altera Corporation Contents ® December 1996 About this Quick Reference Guide...............................................................................................................iii How to Contact Altera ..........................................................................................................................iii Typographic Conventions ....................................................................................................................iv Section 1: Introduction ............................................................................................................................... 1 Overview .................................................................................................................................................. 1 History of LPM........................................................................................................................................ 1 LPM Features........................................................................................................................................... 2 LPM Functions ........................................................................................................................................ 2 Section 2: Gate Functions.......................................................................................................................... 3 lpm_and ................................................................................................................................................... 4 lpm_bustri............................................................................................................................................ 5 lpm_clshift ......................................................................................................................................... 6 lpm_constant ....................................................................................................................................... 7 lpm_decode............................................................................................................................................ 8 lpm_inv ................................................................................................................................................... 9 lpm_mux ................................................................................................................................................. 10 busmux ................................................................................................................................................... 11 mux .......................................................................................................................................................... 12 lpm_or ................................................................................................................................................... 13 lpm_xor ................................................................................................................................................. 14 Section 3: Arithmetic Functions ............................................................................................................ 15 lpm_abs ................................................................................................................................................. 16 lpm_add_sub ....................................................................................................................................... 17 lpm_compare ....................................................................................................................................... 19 lpm_counter ....................................................................................................................................... 21 lpm_mult .............................................................................................................................................. 23 Altera Corporation v Contents Section 4: Storage Functions ................................................................................................................. 25 lpm_ff ................................................................................................................................................... 26 lpm_latch ............................................................................................................................................ 28 lpm_ram_dq ......................................................................................................................................... 29 lpm_ram_io ......................................................................................................................................... 31 lpm_rom ................................................................................................................................................. 33 lpm_shiftreg..................................................................................................................................... 34 Section 5: Custom Parameterized Functions ................................................................................... 37 csfifo ................................................................................................................................................... 38 csdpram ................................................................................................................................................. 39 Section 6: Altera Sales Offices .............................................................................................................. 41 Altera Regional Offices ........................................................................................................................ 41 Altera International Sales Offices ....................................................................................................... 42 Altera Corporation vi Introduction ® December 1996 Overview Digital logic designers today must create designs consisting of tens-ofthousands of gates while meeting increased pressure to shorten time-tomarket. At the same time, designers must maintain architectureindependence without sacrificing silicon efficiency. Meeting these requirements with today’s EDA software tools is not easy. Schematic-based design entry provides superior efficiency but implements architecture-dependent, low-level functions. High-level hardware description languages (HDLs) offer architecture-independence, but offer reduced silicon efficiency and performance. Because a standard set of functions supported by all EDA and integrated circuit (IC) vendors was not previously available, bridging the gap between architecture-independence and efficiency was difficult. However, with the introduction of EDA software tools that support the library of parameterized modules (LPM), designers can now create architecture-independent designs that have high silicon efficiency. History of LPM The LPM standard was proposed in 1990 to enable efficient mapping of digital designs to diverse architectures such as programmable logic devices (PLDs), gate arrays, and standard cells. The LPM was accepted as an Electronic Industries Association (EIA) Interim standard in April 1993 as an adjunct standard to the Electronic Design Interface Format (EDIF), an industry-standard syntax that describes a structural netlist. EDIF can be used to transfer designs between the different software tools of EDA vendors and from EDA tools to IC tools. LPM functions describe the logical operation of the netlist. LPM functions used in a design can be directly passed to the IC vendor’s design implementation software through an EDIF netlist file. Before the arrival of the LPM standard, each EDIF netlist would typically contain architecture-specific logic functions, which made architecture-independent design impossible. LPM functions are compatible with any text or graphic design entry tool, and are supported by Altera® through MAX+PLUS® II and major EDA tool vendors, including Cadence, Exemplar, Mentor Graphics, MINC, Summit Design, Synopsys, VeriBest, and Viewlogic. Altera has supported the standard since 1993, and many other silicon companies will support the LPM standard by the end of 1997. Altera Corporation 1 Introduction LPM Features The primary objective for the LPM is to enable architecture-independent design without sacrificing efficiency. The LPM meets the following key criteria: s Architecture-independent design entry—Designers can work with LPM functions during design entry and verification without specifying the target architecture. Design entry and simulation tools remain architecture-independent, relying on the synthesis or fitting tools to efficiently map the design to various architectures. Efficient design mapping—The LPM allows designers to create architecture-independent designs without sacrificing efficiency. The IC vendor is responsible for the mapping of LPM functions; thus, optimum solutions are guaranteed. Tool-independent design entry—The LPM enables designers to migrate designs between EDA tools while maintaining a high-level logic description of the functions. For example, designers can use one vendor’s tool for logic synthesis and another vendor’s tool for logic simulation. Specification of a complete design—LPM functions completely specify the digital logic for any design. Designers can create new functions with LPM functions. s s s LPM Functions The LPM presently contains 25 functions. Despite its small size, the LPM can duplicate the functionality of other design libraries that contain many more functions; each function contains parameters that allow it to expand in many dimensions. For example, the lpm_counter function allows the user to create counters with widths ranging from 1 to 256 bits. In addition to width, the user can specify the features and functionality of the counter. For example, parameters indicate whether the counter counts up or down, or loads synchronously or asynchronously. Thus, the single lpm_counter function can replace over thirty 74-series counters. 2 Altera Corporation Gate Functions ® December 1996 lpm_and ............................................................................................................................................................4 lpm_bustri.....................................................................................................................................................5 lpm_clshift ..................................................................................................................................................6 lpm_constant ................................................................................................................................................7 lpm_decode.....................................................................................................................................................8 lpm_inv ............................................................................................................................................................9 lpm_mux ..........................................................................................................................................................10 busmux ............................................................................................................................................................11 mux ...................................................................................................................................................................12 lpm_or ............................................................................................................................................................13 lpm_xor ..........................................................................................................................................................14 Altera Corporation 3 Gate Functions lpm_and Parameterized AND Gate LPM_AND data result LPM_SIZE= LPM_WIDTH= Ports Name data result Type Input Output Required Yes Yes Description Data input to the AND gate(s). This port consists of LPM_SIZE buses, each LPM_WIDTH wide. Each result bit is the AND of all data[LPM_SIZE–1..0] inputs. This port is LPM_WIDTH wide. Parameters Name LPM_SIZE LPM_WIDTH Required Yes Yes Value Integer > 0 Integer > 0 Description Number of inputs to each AND gate. Width of the result port. Number of AND gates. 4 Altera Corporation Gate Functions lpm_bustri LPM_BUSTRI enabledt data tridata enabletr result LPM_WIDTH= Parameterized Tri-State Buffer The lpm_bustri function can be used to create both unidirectional and bidirectional tri-state bus controllers. Ports Name data enabletr enabledt result tridata Type Input Input Input Output Bidirectional Required Yes No Yes No Yes Description Data input to the tridata bus. This port is LPM_WIDTH wide. If high, enables tridata onto the result bus. Required if result is present (default = 0). If high, enables data onto the tridata bus. This port is LPM_WIDTH wide. Bidirectional bus signal. This port is LPM_WIDTH wide. Parameters Name LPM_WIDTH Required Yes Value Integer > 0 Description Width of the data, result, and tridata ports. Altera Corporation 5 Gate Functions lpm_clshift Parameterized Combinatorial Logic Shifter or Barrel Shifter The lpm_clshift function performs logical, rotational, or arithmetic combinatorial shifting. The direction and distance of the shifting are usercontrollable. LPM_CLSHIFT data result distance underflow direction overflow LPM_SHIFTTYPE= LPM_WIDTH= LPM_WIDTHDIST=CEIL(LOG2(LPM_WIDTH)) Ports Name data distance direction Type Input Input Input Required Yes Yes No Description Data to be shifted. This port is LPM_WIDTH wide. Number of positions to shift data in the direction specified by the direction port. This port is LPM_WIDTHDIST wide. Direction of shift. Low = left (toward the most significant bit (MSB)), high = right (toward the least significant bit (LSB)). Default value is 0 (low) = left (toward the MSB). Shifted data. This port is LPM_WIDTH wide. Logical or arithmetic underflow. If "ROTATE" is specified as the LPM_SHIFTTYPE parameter value and overflow and underflow are connected, the output of overflow and underflow will be undefined logic levels. Logical or arithmetic overflow. If "ROTATE" is specified as the LPM_SHIFTTYPE parameter value and overflow and underflow are connected, the output of overflow and underflow will be undefined logic levels. result underflow Output Output Yes No overflow Output No Parameters Name LPM_SHIFTTYPE Required No Value Description The sign bit is extended for "ARITHMETIC" right shifts. For "LOGICAL" a "LOGICAL" right shift, 0s are always shifted into the "ROTATE" "ARITHMETIC" MSB or LSB. The default value is "LOGICAL". Integer > 1 Integer > 0 Width of the data and result ports. Width of the distance port. The distance port values normally range from 0, which is “no shift,” to (LPM_WIDTH – 1), which is the maximum meaningful shift. The typical value assigned to LPM_WIDTHDIST is “the smallest integer not less than log2(LPM_WIDTH)” or ceil(log2(LPM_WIDTH)). Any distance port value greater than (LPM_WIDTH – 1) results in an undefined logic level. LPM_WIDTH LPM_WIDTHDIST Yes Yes 6 Altera Corporation Gate Functions lpm_constant Parameterized Constant Generator The lpm_constant function applies a constant to a bus. This function is useful for comparisons and arithmetic functions that operate on a constant value. LPM_CONSTANT result (cvalue) LPM_CVALUE= LPM_WIDTH= Ports Name result Type Output Required Yes Description Value specified by the argument to LPM_CVALUE. This port is LPM_WIDTH wide. The LPM_CVALUE parameter is truncated or zero-padded to LPM_WIDTH bits. Parameters Name LPM_CVALUE Required Yes Value Integer ≥ 0 Description Constant value to be driven out on the result port. If LPM_CVALUE cannot be represented in LPM_WIDTH bits, the result port drives the value LPM_CVALUE mod 2LPM_WIDTH. Width of the result port. LPM_WIDTH Yes Integer > 0 Altera Corporation 7 Gate Functions lpm_decode Parameterized Decoder LPM_DECODE clock aclr data enable LPM_DECODES=2^LPM_WIDTH LPM_PIPELINE= LPM_WIDTH= eq Ports Name clock Type Input Required No Description Clock for pipelined usage. The clock port provides pipelined operation for lpm_decode. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected. Asynchronous clear for pipelined usage. The pipeline initializes to undefined. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock. Data input. Treated as an unsigned binary-encoded number. This port is LPM_WIDTH wide. Enable. All outputs are low when this port is inactive. If absent, the default value is active (high). Output of the decoder. This port is LPM_DECODES wide. If data ≥ LPM_DECODES, all eq outputs are 0. aclr Input No data enable eq Input Input Output Yes No Yes Parameters Name LPM_DECODES LPM_PIPELINE Required Yes No Value Description 2LPM_WIDTH ≥ Integer > 0 Number of explicit decoder outputs. The default value is 2LPM_WIDTH. Integer ≥ 0 Specifies the number of clock cycles of latency associated with the eq output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. The default value is 0 (non-pipelined). Width of the input value to be decoded. LPM_WIDTH Yes Integer > 0 8 Altera Corporation Gate Functions lpm_inv Parameterized Inverter data LPM_WIDTH= LPM_INV result Ports Name data result Type Input Output Required Yes Yes Description Data input to the lpm_inv function. This port is LPM_WIDTH wide. Inverted result. This port is LPM_WIDTH wide. Parameters Name LPM_WIDTH Required Yes Value Integer > 0 Description Width of the data and result ports. Altera Corporation 9 Gate Functions lpm_mux Parameterized Multiplexer LPM_MUX aclr data result clock sel LPM_PIPELINE= LPM_SIZE= LPM_WIDTH= LPM_WIDTHS=CEIL(LOG2(LPM_SIZE)) Ports Name aclr Type Input Required No Description Asynchronous clear for pipelined usage. The pipeline initializes to undefined. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to the clock. Data input. This port consists of LPM_SIZE buses, each LPM_WIDTH wide. Clock for pipelined usage. The clock port provides pipelined operation for lpm_mux. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected. Selects one of the input buses. This port is LPM_WIDTHS wide. Selected input port. This port is LPM_WIDTH wide. data clock Input Input Yes Yes sel result Input Output Yes Yes Parameters Name LPM_PIPELINE Required No Value Integer ≥ 0 Description Specifies the number of clock cycles of latency associated with the result output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. The default value is 0 (non-pipelined). LPM_SIZE LPM_WIDTH LPM_WIDTHS Yes Yes Yes 2LPM_WIDTHS ≥ Integer > 1 Number of inputs to each multiplexer. Number of input buses. Integer > 0 Integer > 0 Width of the data and result ports. Width of the sel port. The default value is ceil(log2(LPM_SIZE)). 10 Altera Corporation Gate Functions busmux Parameterized Multiplexer The busmux function is an Altera-provided function derived from lpm_mux and is intended to simplify the use of lpm_mux in Graphic Design Files (.gdf). The busmux function is an instance of lpm_mux with LPM_SIZE set to 2. WIDTH= BUSMUX dataa 0 result datab 1 sel Ports Name dataa datab sel result Type Input Input Input Output Required Yes Yes Yes Yes Description Data input to the busmux. This port is WIDTH wide. Data input to the busmux. This port is WIDTH wide. Selects one of the ports. The selected input port. This port is WIDTH wide. Parameters Name WIDTH Required Yes Value Integer > 0 Description Width of the dataa, datab, and result ports. Altera Corporation 11 Gate Functions mux Parameterized Multiplexer data MUX result WIDTH= WIDTHS=CEIL(LOG2(WIDTH)) The mux function is an Altera-provided function derived from lpm_mux and is intended to simplify the use of lpm_mux in GDFs. The mux function is an instance of lpm_mux with LPM_WIDTH set to 1. sel Ports Name data sel result Type Input Input Output Required Yes Yes Yes Description Data input to the mux. This port is WIDTH wide. Selects one of the ports. This port is WIDTHS wide. The selected input port. This port is 1 bit wide. Parameters Name WIDTH WIDTHS Required Yes Yes Value Integer > 0 Integer > 0 Description Width of the data port. Width of the sel port. The default value is ceil(log2(WIDTH)). 12 Altera Corporation Gate Functions lpm_or Parameterized OR Gate data LPM_OR result LPM_WIDTH= LPM_SIZE= Ports Name data result Type Input Output Required Yes Yes Description Data input to the OR gate(s). This port consists of LPM_SIZE buses, each LPM_WIDTH wide. Result of OR operators. This port is LPM_WIDTH wide. Parameters Name LPM_WIDTH LPM_SIZE Required Yes Yes Value Integer > 0 Integer > 0 Description Width of the data and result ports. Number of OR gates. Number of inputs to each OR gate. Number of input buses. Altera Corporation 13 Gate Functions lpm_xor Parameterized XOR Gate data LPM_XOR result LPM_SIZE= LPM_WIDTH=1 Ports Name data result Type Input Output Required Yes Yes Description Data input to the XOR gate(s). This port consists of LPM_SIZE buses, each LPM_WIDTH wide. Each result bit is the XOR of LPM_SIZE bits. This port is LPM_WIDTH wide. Parameters Name LPM_SIZE LPM_WIDTH Required Yes Yes Value Integer > 0 Integer > 0 Description Number of inputs to each XOR gate. Number of input buses. Width of the data and result ports. Number of XOR gates. 14 Altera Corporation Arithmetic Functions ® December 1996 lpm_abs ......................................................................................................................................................... 16 lpm_add_sub ............................................................................................................................................... 17 lpm_compare ............................................................................................................................................... 19 lpm_counter ................................................................................................................................................21 lpm_mult .......................................................................................................................................................23 Altera Corporation 15 Arithmetic Functions lpm_abs Parameterized Absolute Value LPM_WIDTH= LPM_ABS data result overflow Ports Name data result overflow Type Input Output Output Required Yes Yes No Description Signed number. This port is LPM_WIDTH wide. Absolute value of data. This port is LPM_WIDTH wide. High if data = –2(LPM_WIDTH – 1). Two’s complement allows one more negative number than positive. The overflow port detects that singular instance and goes high to indicate that no positive equivalent exists. Parameters Name LPM_WIDTH Required Yes Value Integer ≥ 0 Description Width of the data and result ports. 16 Altera Corporation Arithmetic Functions lpm_add_sub Parameterized Adder/Subtractor LPM_ADD_SUB add_sub cin dataa clock datab overflow aclr cout result LPM_DIRECTION= LPM_PIPELINE= LPM_REPRESENTATION= LPM_WIDTH= ONE_INPUT_IS_CONSTANT= Ports Name add_sub Type Input Required No Description If the input is high, the operation = dataa + datab. If the input is low, the operation = dataa – datab. This port cannot be used if the LPM_DIRECTION parameter is used. If both the add_sub port and the LPM_DIRECTION parameter are omitted, the operation defaults to "ADD". Carry-in to the low-order bit. If the operation is "ADD", Low = 0 and High = +1. If the operation is "SUB", Low = –1 and High = 0. If omitted, the default is 0 (i.e., no affect on "ADD" or "SUB" operations). Augend/Minuend. This port is LPM_WIDTH wide. Clock for pipelined usage. The clock port provides pipelined operation of lpm_add_sub. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected. Addend/Subtrahend. This port is LPM_WIDTH wide. Asynchronous clear for pipelined usage. The pipeline initializes to undefined. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to clock. dataa + or – datab + or – cin. This port is LPM_WIDTH wide. Result exceeds available precision. If overflow is used, cout cannot be used. The overflow signal has a physical interpretation as the XOR of the carry into the MSB with the carry out of the MSB. The overflow signal is only meaningful when the LPM_REPRESENTATION parameter is set to "SIGNED". Note (1) Carry-out (borrow-in) of the MSB. If overflow is used, cout cannot be used. The cout signal has a physical interpretation as the carry-out (borrow-in) of the MSB and is most meaningful for detecting overflow in "UNSIGNED" operations. Note (2) cin Input No dataa clock Input Input Yes No datab aclr Input Input Yes No result overflow Output Output Yes No cout Output No Altera Corporation 17 Arithmetic Functions Parameters Name LPM_DIRECTION Required No Value "ADD" "SUB" "DEFAULT" Integer ≥ 0 Description The add_sub port cannot be used if the LPM_DIRECTION parameter is has a value other than "DEFAULT". The default value is "DEFAULT". Specifies the number of clock cycles of latency associated with the result output. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. The default value is 0 (non-pipelined). LPM_PIPELINE No LPM_REPRESENTATION LPM_WIDTH ONE_INPUT_IS_CONSTANT No Yes No "SIGNED" Type of addition performed. The default value is "SIGNED". "UNSIGNED" Integer > 0 "YES" "NO" Width of the dataa, datab, and result ports. Provides greater optimization if an input is constant. The default value is "NO". Notes: (1) The following table describes the overflow port during "ADD" and "SUB" operations. Value "UNSIGNED" "SIGNED" Not meaningful. (dataa + datab + cin) > 2(LPM_WIDTH – 1) – 1 or (dataa + datab + cin) > 2(LPM_WIDTH – 1) ADD Operation Not meaningful. SUB Operation (dataa – datab – cin) > 2(LPM_WIDTH – 1) – 1 or (dataa – datab – cin) > 2(LPM_WIDTH – 1) (2) The following table describes the cout port during "ADD" and "SUB" operations. Value "UNSIGNED" "SIGNED" ADD Operation dataa + datab + cin > 2 (LPM_WIDTH – 1) – 1 SUB Operation Normal subtract. However, if cout = 0, then (dataa – datab – cin) < 0. Normal result of adding two negative numbers, Normal result when subtracting a positive or possible overflow. number from a negative number, or possible overflow. 18 Altera Corporation Arithmetic Functions lpm_compare Parameterized Comparator LPM_COMPARE alb aeb agb ageb aneb aleb CHAIN_SIZE= LPM_PIPELINE= LPM_REPRESENTATION= LPM_WIDTH= ONE_INPUT_IS_CONSTANT= dataa datab clock aclr Ports Name dataa datab clock Type Input Input Input Required Yes Yes No Description The datab signal is compared to this value. This port is LPM_WIDTH wide. Value to be compared to dataa. This port is LPM_WIDTH wide. Clock for pipelined usage. The clock port provides pipelined operation for lpm_compare. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected. Asynchronous clear for pipelined usage. The pipeline initializes to undefined. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to clock. High (1) if dataa < datab. One of the alb, aeb, agb, ageb, aleb, or aneb outputs must be present. High (1) if dataa = datab. One of the alb, aeb, agb, ageb, aleb, or aneb outputs must be present. High (1) if dataa > datab. One of the alb, aeb, agb, ageb, aleb, or aneb outputs must be present. High (1) if dataa ≥ datab. One of the alb, aeb, agb, ageb, aleb, or aneb outputs must be present. High (1) if dataa ≠ datab. One of the alb, aeb, agb, ageb, aleb, or aneb outputs must be present. High (1) if dataa ≤ datab. One of the alb, aeb, agb, ageb, aleb, or aneb outputs must be present. aclr Input No alb aeb agb ageb aneb aleb Output Output Output Output Output Output No No No No No No Altera Corporation 19 Arithmetic Functions Parameters Name CHAIN_SIZE Required No Value Integer > 0 Description Maximum allowable length of carry chains or cascade chains in FLEX 10K and FLEX 8000 devices. The default value is 8. In MAX+PLUS II, this value overrides the value of the Max. Auto Length option for the Carry Chain or Cascade Chain logic option(s) in the global project logic synthesis style, which is specified with the Global Project Logic Synthesis dialog box (Assign menu). For other device families, varying the CHAIN_SIZE parameter will provide different speed/size combinations—setting smaller values for CHAIN_SIZE generally results in faster and larger comparators and vice versa. For more information, contact Altera Applications. Specifies the number of clock cycles of latency associated with the alb, aeb,agb, ageb, aneb, and aleb outputs. A value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. Default value is 0 (non-pipelined). LPM_PIPELINE No Integer ≥ 0 LPM_REPRESENTATION LPM_WIDTH ONE_INPUT_IS_CONSTANT No Yes No "SIGNED" Type of comparison performed. The default value is "UNSIGNED" "UNSIGNED". Integer > 0 "YES" "NO" Width of the dataa and datab ports. Provides greater optimization if an input is constant. The default value is "NO". 20 Altera Corporation Arithmetic Functions lpm_counter Parameterized Counter The lpm_counter function is a fullfeatured counter with loading, up/down control, clock, and count enabling and clearing. LPM_COUNTER sset sload updown cnt_en data clock clk_en sconst sclr LPM_SVALUE= LPM_AVALUE= LPM_MODULUS= LPM_DIRECTION= LPM_WIDTH= q eq Ports (Part 1 of 2) Name sset Type Input Required No Description Synchronous set input. Sets the counter on the next active clock edge. Default = 0. Sets q outputs to all 1s, or to the value specified by LPM_SVALUE. If both sset and sclr are used and both are asserted, sclr is dominant. For outputs such as q and eq, sset affects the output before polarity is applied. Synchronous load input. Loads the counter with data on the next active clock edge. Default = 0. If sload is used, data must be connected. Controls the direction of the count. High (1) = count up. Low (0) = count down. Default = up (1). If the LPM_DIRECTION parameter is used, the updown port cannot be connected. If LPM_DIRECTION is not used, the updown port is optional. Count enable input. Disables count when low (0) without affecting sload, sset, or sclr. Default = 1. Parallel data input to the counter. This port is LPM_WIDTH wide. Uses aload and/or sload. Positive-edge-triggered clock. Clock enable input. Enables all synchronous activities. Default = 1. This port is provided only for backwards-compatibility in MAX+PLUS II pre-version 6.0 designs. Altera does not recommend using this port for new designs. Synchronous clear input. Clears the counter on the next active clock edge. Default = 0. If both sset and sclr are used and both are asserted, sclr is dominant. For outputs such as q and eq, sclr affects the output before polarity is applied. sload updown Input Input No No cnt_en data clock clk_en sconst Input Input Input Input Input No No Yes No No sclr Input No Altera Corporation aset aclr aload aconst 21 Arithmetic Functions Ports (Part 2 of 2) Name aset Type Input Required No Description Asynchronous set input. Default = 0. Sets q outputs to all 1s, or to the value specified by LPM_AVALUE. If both aset and aclr are used and both are asserted, aclr is dominant. For outputs such as q and eq, aset affects the output before polarity is applied. Asynchronous clear input. Default = 0. If both aset and aclr are used and both are asserted, aclr is dominant. For outputs such as q and eq, aclr affects the output before polarity is applied. Asynchronous load input. Asynchronously loads the counter with the value on the data input. Default = 0. If aload is used, data must be used. This port is provided only for backwards-compatibility in MAX+PLUS II pre-version 6.0 designs. Altera does not recommend using this port in new designs. Counter decode output. Active high when the counter reaches the specified count value. Either the q port or eq port must be connected. Up to c eq ports can be used (c ≤ 15). Only the 16 lowest count values are decoded. When the count value is c, the eqc output is set high (1). For example, when the count is 0, eq0 = 1, when the count is 1, eq1 = 1, and when the count is 15, eq15 = 1. Decoded outputs for count values of 16 or greater require external decoding. The eqc outputs are asynchronous. Data output from the counter. This port is LPM_WIDTH wide. Either q or at least one of the eq ports must be connected. aclr Input No aload aconst Input Input No No eq Output No q Output No Parameters Name LPM_SVALUE LPM_AVALUE Required No No Value Integer ≥ 0 Integer ≥ 0 Description Constant value that is loaded on the rising edge of clock when sset is high. Must be used if sset is used. Constant value that is loaded when aset is high. This parameter must be used if aset is used. If the value specified is larger than the <modulus>, the behavior of the counter is an undefined logic level. The <modulus> is LPM_MODULUS, if present, or 2LPM_WIDTH. The maximum count, plus one. Number of unique states in the counter’s cycle. If the load value is larger than the LPM_MODULUS parameter, the behavior of the counter is not specified. The default value is 2LPM_WIDTH. If the LPM_DIRECTION parameter is used, the updown port cannot be connected. When the updown port is not connected, the count direction is "UP". In all other cases, the default value is "DEFAULT". Width of the input and output ports. If no output ports are specified, the value is the number of bits in the count. LPM_MODULUS No Integer > 1 LPM_DIRECTION No "UP" "DOWN" "DEFAULT" Integer > 0 LPM_WIDTH Yes 22 Altera Corporation Arithmetic Functions lpm_mult Parameterized Multiplier The lpm_mult function allows two signed or unsigned numbers to be multiplied. In addition, the result of the multiplication can be added to a third number. INPUT_A_IS_CONSTANT= INPUT_B_IS_CONSTANT= LPM_PIPELINE= LPM_REPRESENTATION= LPM_WIDTHA= LPM_WIDTHB= LPM_WIDTHP=(LPM_WIDTHA+LPM_WIDTHB) LPM_WIDTHS=LPM_WIDTHA LPM_MULT clock dataa sum datab aclr result Ports Name clock Type Input Required No Description Clock for pipelined usage. The clock port provides pipelined operation for lpm_mult. For LPM_PIPELINE values other than 0 (default value), the clock port must be connected. Multiplicand. This port is LPM_WIDTHA wide. Partial sum. This port is LPM_WIDTHS wide. Multiplier. This port is LPM_WIDTHB wide. Asynchronous clear for pipelined usage. The pipeline initializes to undefined. The aclr port can be used at any time to reset the pipeline to all 0s, asynchronously to clock. This port is LPM_WIDTHP wide. If LPM_WIDTHP < max (LPM_WIDTHA + LPM_WIDTHB, LPM_WIDTHS) or ( LPM_WIDTHS), only the LPM_WIDTHP MSBs are present. dataa sum datab aclr Input Input Input Input Yes No Yes No result Output Yes Altera Corporation 23 Arithmetic Functions Parameters Name INPUT_A_IS_CONSTANT Required No Value "YES" "NO" "YES" "NO" Integer ≥ 0 Description If dataa is connected to a constant value, setting the value of INPUT_A_IS_CONSTANT to "YES" optimizes the multiplier for resource usage and speed. The default value is "NO". If datab is connected to a constant value, setting the value of INPUT_B_IS_CONSTANT to "YES" optimizes the multiplier for resource usage and speed. The default value is "NO". Specifies the number of clock cycles of latency associated with the result output. The default value of zero (0) indicates that no latency exists, and that a purely combinatorial function will be instantiated. The default value is 0 (non-pipelined). INPUT_B_IS_CONSTANT No LPM_PIPELINE No LPM_REPRESENTATION LPM_WIDTHA LPM_WIDTHB LPM_WIDTHP LPM_WIDTHS No Yes Yes Yes No Type of multiplication performed. The default value is "SIGNED" "UNSIGNED" "UNSIGNED". Integer > 0 Integer > 0 Integer > 0 Integer > 0 Width of the dataa port. Width of the datab port. Width of the result port. The default is LPM_WIDTHA+LPM_WIDTHB. Width of the sum port. If the sum port is not used, LPM_WIDTHS must be set to a value between 1 and LPM_WIDTHP, inclusive. The default value is LPM_WIDTHA. Same as LPM_PIPELINE. LATENCY, Note (1) No Integer ≥ 0 Note: (1) The LATENCY parameter is provided only for backwards-compatibility with MAX+PLUS II pre-version 7.0 designs. For all new designs, you should use the LPM_PIPELINE parameter instead. 24 Altera Corporation Storage Functions ® December 1996 lpm_ff ............................................................................................................................................................26 lpm_latch .....................................................................................................................................................28 lpm_ram_dq...................................................................................................................................................29 lpm_ram_io...................................................................................................................................................31 lpm_rom ..........................................................................................................................................................33 lpm_shiftreg ..............................................................................................................................................34 Altera Corporation 25 Storage Functions lpm_ff Parameterized D or T Flipflop LPM_FF aset aload sset sload data clock enable sclr aclr LPM_AVALUE= LPM_FFTYPE= LPM_SVALUE= LPM_WIDTH= q Ports Name aload sset Type Input Input Required No No Description Asynchronous load input. Asynchronously loads the flipflop with the value on the data input. Default = 0. If aload is used, data must be used. Synchronous set input. Sets the q outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1s. If both sset and sclr are used and both are asserted, sclr is dominant. The sset input affects the output q values before polarity is applied to the ports. Synchronous load input. Loads the flipflop with the value on the data input on the next active clock edge. Default = 0. If sload is used, data must be used. For load operation, sload must be high (1) and enable must be high (1) or unconnected. T flipflop: toggle enable; D flipflop: data input. This port is LPM_WIDTH wide. If the data port is not used, at least one of the aset, aclr, sset, or sclr ports must be used. Positive-edge-triggered clock. Clock enable input. Default = 1. Synchronous clear input. If both sset and sclr are used and both are asserted, sclr is dominant. The sclr input affects the output q values before polarity is applied to the ports. Asynchronous set input. Sets q outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q outputs to all 1s. Asynchronous clear input. If both aset and aclr are used and both are asserted, aclr is dominant. The aclr input affects the output q values before polarity is applied to the ports. Data output from D flipflops. This port is LPM_WIDTH wide. sload Input No data Input No clock enable sclr Input Input Input Yes No No aset aclr Input Input No No q Output Yes 26 Altera Corporation Storage Functions Parameters Name LPM_AVALUE LPM_FFTYPE LPM_SVALUE LPM_WIDTH Required Yes No No Yes Value Integer ≥ 0 "DFF" "TFF" Integer ≥ 0 Integer > 0 Description Constant value that is loaded when aset is high. The default value is all 1s. Type of flipflop. The default value is "DFF". Constant value that is loaded on the rising edge of clock when sset is high. The default value is all 1s. Width of the data and q ports. Altera Corporation 27 Storage Functions lpm_latch Parameterized Latch LPM_LATCH aset q data gate aconst aclr LPM_WIDTH= LPM_AVALUE= Ports Name aset Type Input Required No Description Asynchronous set input. Default = 0. Sets q outputs to the value specified by LPM_AVALUE, if that value is present. If no LPM_AVALUE is specified, aset will set the count to all 1s. If both aset and aclr are used and both are asserted, aclr is dominant. The aset and aclr inputs affect the output q values before polarity is applied to the ports. Data input to the D-type latch. This port is LPM_WIDTH wide. If the data port is not used, either aset or aclr must be used. Latch enable input. High = flow-through, low = latch. This port is provided only for backwards-compatibility in MAX+PLUS II pre-version 6.0 designs. Altera does not recommend using this port in new designs. Asynchronous clear input. Default = 0. Sets the latch to all 0s. If both aset and aclr are used and both are asserted, aclr is dominant. The aset and aclr inputs affect the output q values before the polarity is applied to the ports. Data output from the latches. This port is LPM_WIDTH wide. data gate aconst Input Input Input No Yes No aclr Input No q Output Yes Parameters Name LPM_WIDTH LPM_AVALUE Required Yes No Value Integer > 0 Integer ≥ 0 Description Width of the data and q ports. Constant value that is loaded when aset is high. The default value of LPM_AVALUE is all 1s. 28 Altera Corporation Storage Functions lpm_ram_dq Parameterized Random Access Memory with Separate Input and Output Ports The lpm_ram_dq function can be used as either synchronous or asynchronous random access memory. The lpm_ram_dq function has separate input and output data buses. LPM_RAM_DQ data address inclock outclock we LPM_ADDRESS_CONTROL= LPM_FILE= LPM_INDATA= LPM_NUMWORDS= LPM_OUTDATA="UNREGISTERED" LPM_WIDTH= LPM_WIDTHAD= q Ports Name data address inclock Type Input Input Input Required Yes Yes No Description Data input to memory. This port is LPM_WIDTH wide. Address input to the memory. This port is LPM_WIDTHAD wide. Synchronizes memory loading. If the inclock port is used, the we port acts as an enable for write operations synchronized to the rising edge of the inclock input. If the inclock port is not used, the we port acts as an enable for asynchronous write operations. Synchronizes q outputs from memory. The addressed memory content q response is synchronous when the outclock port is connected, and asynchronous when it is not connected. Write enable input. When high, enables write operation to the memory. Required if inclock is not present. If only we is used, the data on the address port should not change while we is high. If the data on the address port changes while we is high, all memory locations that are addressed are overwritten with data. Data output from the memory. This port is LPM_WIDTH wide. outclock Input No we Input Yes q Output Yes Altera Corporation 29 Storage Functions Parameters Name LPM_ADDRESS_CONTROL LPM_FILE Required No No Value Description "REGISTERED" Controls whether the address and we ports are "UNREGISTERED" registered. The default value is "REGISTERED". "<filename>" Name of the Memory Initialization File (.mif) or Hexadecimal File (.hex) containing RAM initialization data ("<filename>"). If omitted, contents default to all 0s. LPM_INDATA LPM_NUMWORDS No No "REGISTERED" Controls whether the data port is registered. The "UNREGISTERED" default value is "REGISTERED". Integer > 0 Number of words stored in memory. In general, this value should be (but is not required to be): 2LPM_WIDTHAD – 1 < LPM_NUMWORDS ≤ 2LPM_WIDTHAD. The default value is 2LPM_WIDTHAD. LPM_OUTDATA LPM_WIDTH LPM_WIDTHAD No Yes Yes "REGISTERED" Controls whether the q and internal eq ports are "UNREGISTERED" registered. The default value is "REGISTERED". Integer > 0 Integer > 0 Width of the data and q ports. Width of the address port. LPM_WIDTHAD should be (but is not required to be): log2(LPM_NUMWORDS). If LPM_WIDTHAD is too small, some memory locations will not be addressable. If LPM_WIDTHAD is too large, the addresses that are too high will return undefined logic levels. 30 Altera Corporation Storage Functions lpm_ram_io Parameterized Random Access Memory with a Single I/O Port The lpm_ram_io function can be used as either synchronous or asynchronous random access memory. The lpm_ram_io function has a bidirectional bus. LPM_RAM_IO address inclock outclock we outenab memenab LPM_ADDRESS_CONTROL= LPM_FILE= LPM_INDATA= LPM_NUMWORDS= LPM_OUTDATA="UNREGISTERED" LPM_WIDTH= LPM_WIDTHAD= dio Ports Name Type Required Yes No Description Address input to the memory. This port is LPM_WIDTHAD wide. If memenab is used, it should be inactive when address is changing. Synchronizes memory loading. If the inclock port is used, the we port acts as an enable for write operations synchronized to the rising edge of the inclock input. If the inclock port is not used, the we port acts as an enable for asynchronous write operations. Synchronizes dio from memory. The addressed memory content q response is synchronous when the outclock port is connected, and asynchronous when it is not connected. Write enable input. Either we or outenab should be used. When high, enables write operations to the memory. If no clock ports are used, the data on the address port should not change when we is high (1). Required if clock is not present. If we is absent, the default value is enabled. Output enable input. High (1): dio from memory address. Low (0): Memory address from dio. Either memenab or outenab must be present. Memory output tri-state enable. Either memenab or outenab must be connected. If memenab is present, it should be inactive when address is changing. Data port for the memory. This port is LPM_WIDTH wide. address Input inclock Input outclock Input No we Input Yes outenab Input No memenab Input No dio Bidirectional Yes Altera Corporation 31 Storage Functions Parameters Name LPM_ADDRESS_CONTROL LPM_FILE LPM_INDATA LPM_NUMWORDS Required No No No No Value Description "REGISTERED" Controls whether the address, memenab, and we ports "UNREGISTERED" are registered. The default value is "REGISTERED". "<filename>" Name of the MIF or Hex File containing ROM initialization data ("<filename>"). If omitted, contents default to all 0s. "REGISTERED" Controls whether the internal data port is registered. The "UNREGISTERED" default value is "REGISTERED". Integer > 0 Number of words stored in memory. In general, this value should be (but is not required to be): 2LPM_WIDTHAD –1 < LPM_NUMWORDS ≤ 2LPM_WIDTHAD. The default value is 2LPM_WIDTHAD. LPM_OUTDATA LPM_WIDTH LPM_WIDTHAD No Yes Yes "REGISTERED" Controls whether the dio port is registered. The default "UNREGISTERED" value is "REGISTERED". Integer > 0 Integer > 0 Width of dio and internal data and q ports. Width of the address port. LPM_WIDTHAD should be (but is not required to be) equal to log2(LPM_NUMWORDS). If LPM_WIDTHAD is too small, some memory locations will not be addressable. If it is too large, the addresses that are too high will return undefined logic levels. 32 Altera Corporation Storage Functions lpm_rom Parameterized Read-Only Memory The lpm_rom function can be used as either synchronous or asynchronous read-only memory. LPM_ROM address inclock outclock memenab LPM_ADDRESS_CONTROL= LPM_FILE= LPM_NUMWORDS= LPM_OUTDATA="UNREGISTERED" LPM_WIDTH= LPM_WIDTHAD= q Ports Name address inclock Type Input Input Required Yes No Description Address input to the memory. This port is LPM_WIDTHAD wide. Clock for input registers. The address port is synchronous (registered) when the inclock port is connected, and is asynchronous (unregistered) when the inclock port is not connected. Clock for output registers. The addressed memory content q response is synchronous when the outclock port is connected, and is asynchronous when it is not connected. Memory enable input. High = data output on q, Low = high-impedance outputs. Memory output. This port is LPM_WIDTH wide. outclock Input No memenab q Input Output No Yes Parameters Name LPM_ADDRESS_CONTROL LPM_FILE LPM_NUMWORDS Required No Yes No Value Description "REGISTERED" Controls whether the address port is registered. The "UNREGISTERED" default value is "REGISTERED". "<filename>" Integer > 0 Name of the MIF or Hex File containing ROM initialization data ("<filename>"). In general, this value should be (but is not required to be) 2LPM_WIDTHAD–1 < LPM_NUMWORDS ≤ 2LPM_WIDTHAD. The default value is 2LPM_WIDTHAD. LPM_OUTDATA LPM_WIDTH LPM_WIDTHAD No Yes Yes "REGISTERED" Controls whether the q port is registered. The default "UNREGISTERED" value is "REGISTERED". Integer > 0 Integer > 0 Width of the q port. Width of the address port. LPM_WIDTHAD should be (but is not required to be) equal to log2(LPM_NUMWORDS). If LPM_WIDTHAD is too small, some memory locations will not be addressable. If it is too large, the addresses that are too high will return undefined logic levels. Altera Corporation 33 Storage Functions lpm_shiftreg Parameterized Shift Register LPM_SHIFTREG sclr sset shiftin load data clock enable LPM_AVALUE= LPM_DIRECTION= LPM_SVALUE= LPM_WIDTH= shiftout q Ports Name sclr Type Input Required No Description Synchronous clear input. If both sset and sclr are used and both are asserted, sclr is dominant. The sclr input affects the output q values before polarity is applied to the ports. Synchronous set input. Sets q outputs to the value specified by LPM_SVALUE, if that value is present, or sets the q outputs to all 1s. If both sset and sclr are used and both are asserted, sclr is dominant. The sset input affects the output q values before polarity is applied to the ports. Serial shift data input. At least one of the data, aset, aclr, sset, sclr, and/or shiftin ports must be used. Synchronous parallel load. High (1): load operation; low (0): shift operation. Default is low (0) shift operation. For parallel load operation, load must be high (1) and enable must be high or unconnected. Data input to the shift register. This port is LPM_WIDTH wide. At least one of the data, aset, aclr, sset, sclr and/or shiftin ports must be used. Positive-edge-triggered clock. Default = 1. Clock enable input. The shift options also use the enable input for the clock enable. For serial operation, both shiftin and enable must be high. Asynchronous clear input. If both aset and aclr are used and both are asserted, aclr is dominant. The aclr input affects the output q values before polarity is applied to the ports. Asynchronous set input. Sets q outputs to the value specified by LPM_AVALUE, if that value is present, or sets the q outputs to all 1s. If both aset and aclr are used and both are asserted, aclr is dominant. The aset input affects the output q values before polarity is applied to the ports. Serial shift data output. This port is LPM_WIDTH wide. Either q or shiftout or both must be used. Data output from the shift register. This port is LPM_WIDTH wide. Either q or shiftout or both must be used. sset Input No shiftin load Input Input No No data clock enable aclr Input Input Input Input No Yes No No aset Input No shiftout q Output Output No No 34 aclr aset Altera Corporation Storage Functions Parameters Name LPM_AVALUE LPM_DIRECTION LPM_SVALUE LPM_WIDTH Required No No No Yes Value Integer > 0 "LEFT" "RIGHT" Integer ≥ 0 Integer > 0 Description Constant value that is loaded when aset is high. Direction of the shift register. The default value is "LEFT". Constant value that is loaded on the rising edge of clock when sset is high. The default value is all 1s. Width of the data and q ports. Altera Corporation 35 Notes: ® Custom Parameterized Functions December 1996 csfifo ............................................................................................................................................................38 csdpram ..........................................................................................................................................................39 Altera Corporation 37 Custom Parameterized Functions csfifo Cycle-Shared FIFO The csfifo function is a custom function that provides a cycle-shared FIFO with both dynamic and static user threshold level controls. It also offers empty and full flag outputs. CSFIFO data wreq q rreq threshold clock empty clockx2 full clr threshlevel LPM_NUMWORDS= LPM_WIDTH=8 Ports Name data wreq rreq clock clockx2 clr threshlevel q threshold empty full Type Input Input Input Input Input Input Input Required Yes Yes Yes Yes Yes No No Yes No No No Write request. Read request. Positive-edge-triggered clock. Positive-edge-triggered clock. Resets csfifo to empty. Description Data input to the csfifo. This port is LPM_WIDTH wide. Level (number of words) that the threshold output signal asserts. Data output from csfifo. This port is LPM_WIDTH wide. Indicates that csfifo contains greater than the threshlevel number of words. Indicates that csfifo is empty. Indicates that csfifo is full. Output Output Output Output Parameters Name LPM_NUMWORDS Required No Value Integer > 0 Description Number of words stored in memory. In general, this value should be (but is not required to be): 2LPM_WIDTH – 1 < LPM_NUMWORDS ≤ 2LPM_WIDTHAD. The default value is 2LPM_WIDTH. Width of the data and q ports. The default value is 8. LPM_WIDTH Yes Integer > 0 38 Altera Corporation Custom Paramterized Functions csdpram Parameterized Cycle-Shared Dual-Port RAM The csdpram function is a custom function that has two address and two data ports that are cycle-shared. This function also provides a busy flag to indicate that the address on both ports is pointing to the same location and that a port will have priority. CSDPRAM dataa datab addressa addressb wea web clock clockx2 LPM_WIDTH= LPM_WIDTHAD= LPM_NUMWORDS= qa qb busy Ports Name dataa datab addressa addressb wea web clock clockx2 qa qb busy Type Input Input Input Input Input Input Input Input Output Output Output Required Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Description Data input to the memory. This port is LPM_WIDTH wide. Data input to the memory. This port is LPM_WIDTH wide. Address input to the memory. This port is LPM_WIDTHAD wide. Address input to the memory. This port is LPM_WIDTHAD wide. Write enable input. Write enable input. Positive-edge-triggered clock. Positive-edge-triggered clock. Data output from the memory. This port is LPM_WIDTH wide. Data output from the memory. This port is LPM_WIDTH wide. Indicates that addressa = addressb and that dataa is writing data. Parameters Name LPM_WIDTH LPM_WIDTHAD Required Yes Yes Value Integer > 0 Integer > 0 Description Width of the dataa, datab, qa, and qb ports. Width of the addressa and addressb ports. LPM_WIDTHAD should be (but is not required to be) equal to log2(LPM_NUMWORDS). If LPM_WIDTHAD is too small, some memory locations will not be addressable. If it is too large, the addresses that are too high will return undefined logic levels. Number of words stored in memory. In general, this value should be (but is not required to be): 2LPM_WIDTHAD – 1 < LPM_NUMWORDS ≤ 2LPM_WIDTHAD. The default value is 2LPM_WIDTHAD. LPM_NUMWORDS No Integer > 0 Altera Corporation 39 Notes: Altera Sales Offices ® December 1996 Altera Regional Offices NORTHERN CALIFORNIA (CORPORATE HEADQUARTERS) Altera Corporation 2610 Orchard Parkway San Jose, CA 95134-2020 TEL: (408) 894-7000 FAX: (408) 433-3943 (408) 894-7755 Altera Corporation 2290 N. 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Stratus Street, Suite 330-17 Beaverton, OR 97008 TEL: (503) 643-8447 FAX: (503) 644-2345 TEXAS Altera Corporation 5080 Spectrum Drive, Suite 812W Dallas, TX 75248 TEL: (972) 701-2330 FAX: (972) 701-2331 TEXAS (continued) Altera Corporation 9430 Research Boulevard Echelon IV, Suite 400 Austin, TX 78759 TEL: (512) 343-4542 FAX: (512) 418-1186 CANADA Altera Corporation 300 March Road, Suite 601B Kanata, Ontario K2K 2E2 Canada TEL: (613) 599-3141 FAX: (613) 599-3143 Altera International Sales Offices UNITED STATES (CORPORATE HEADQUARTERS) Altera Corporation 2610 Orchard Parkway San Jose, CA 95134-2020 USA TEL: (408) 894-7000 FAX: (408) 433-3943 (408) 894-7755 UNITED KINGDOM (EUROPEAN HEADQUARTERS) Altera UK Limited Holmers Farm Way High Wycombe Buckinghamshire HP12 4XF United Kingdom TEL: (44) 1 494 602 000 FAX: (44) 1 494 602 001 NORTHERN EUROPE Altera UK Limited Holmers Farm Way High Wycombe Buckinghamshire HP12 4XF United Kingdom TEL: (44) 1 494 602 020 FAX: (44) 1 494 602 021 BELGIUM Altera Belgium Katwilgweg 7B 2050 Antwerpen Belgium TEL: (32) 3 254 0420| FAX: (32) 3 254 0320 FRANCE Altera France S.A.R.L. Le Mermoz 13 Avenue Morane Saulnier 78140 Velizy France TEL: (33) 1 34 63 07 50 FAX: (33) 1 34 63 07 51 GERMANY Altera GmbH Max-Planck-Str. 5 D-85716 Unterschleissheim Germany TEL: (49) 89 3218 250 FAX: (49) 89 3218 2579 HONG KONG Altera Hong Kong Suite 1008, Tower 1 China Hong Kong City 33 Canton Road, Tsimshatsui Kowloon, Hong Kong TEL: (852) 2377-0218 FAX: (852) 2377-2811 ITALY Altera Italia S.R.L. Corso Lombardia 75 Autoporto Pescarito 10099 San Mauro, Torinese (Torino) Italy TEL: (39) 11 223 8588 FAX: (39) 11 223 8589 JAPAN Altera Japan, Ltd. Shinjuku Mitsui Building 2-1-1, Nishi-Shinjuku Shinjuku-ku, Tokyo 162-04 Japan TEL: (81) 3 3340 9480 FAX: (81) 3 3340 9487 KOREA Altera Korea Youndang Building, Suite 501 144-23 Samsung-dong, Kangnam-Ku Seoul, Korea 135-090 TEL: (82) 2 538-6895 FAX: (82) 2 538-6896 SWEDEN Altera AB Sjoangsvagen 15 192 72 Sollentuna Sweden TEL: (46) 8 626 60 91 FAX: (46) 8 626 60 99 42 Altera Corporation LPM Quick Reference Guide December 1996 A-CAT-LPM-01 Altera, MAX, MAX+PLUS, MAX+PLUS II, and FLEX are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera Corporation acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog and Cadence are a registered trademark of Cadence Design Systems, Inc. Data I/O is a registered trademark of Data I/O Corporation. Exemplar Logic is a registered trademark of Exemplar Logic, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. MINC is a registered trademark of MINC Incorporated. SPARCstation is a trademark of SPARC International, Inc. and is licensed exclusively to Sun Microsystems, Inc. Sun Workstation is a registered trademark, and Sun is a trademark of Sun Microsystems, Inc. Synopsys is a registered trademark of Synopsys, Inc. VeriBest is a registered trademark of VeriBest Inc. Viewlogic is a registered trademark ot Viewlogic Systems, Inc. Altera reserves the right to make changes, without notice, in the devices or the device specifications identified in this document. Altera advises its customers to obtain the latest version of device specifications to verify, before placing orders, that the information being relied upon by the customer is current. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty. Testing and other quality control techniques are used to the extent Altera deems such testing necessary to support this warranty. Unless mandated by government requirements, specific testing of all parameters of each device is not necessarily performed. In the absence of written agreement to the contrary, Altera assumes no liability for Altera applications assistance, customer’s product design, or infringement of patents or copyrights of third parties by or arising from use of semiconductor devices described herein. Nor does Altera warrant or represent any patent right, copyright, or other intellectual property right of Altera covering or relating to any combination, machine, or process in which such semiconductor devices might be or are used. Altera’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Altera Corporation. As used herein: 1. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Products mentioned in this document are covered by one or more of the following U.S. patents: 5,574,893; 5,572,717; 5,572,148; 5,572,067; 5,570,040; 5,567,177; 5,563,592; 5,557,217; 5,555,214; 5,550,842; 5,550,782; 5,548,552; 5,548,228; 5,543,732; 5,543,730; 5,541,530; 5,537,295; 5,537,057; 5,525,917; 5,523.247; 5,517,186; 5,498,975; 5,495,182; 5,493,519; 5,477,474; 5,463,328; 5,444,394; 5,438,295; 5,436,575; 5,436,574; 5,434,514; 5,432,467; 5,414,312; 5,399,922; 5,384,499; 5,376,844; 5,375,086; 5,371,422; 5,369,314; 5,359,243; 5,359,242; 5,353,248; 5,352,940; 5,350,954; 5,349,255; 5,341,308; 5,341,048; 5,341,044; 5,329,487; 5,317,212; 5,317,210; 5,315,172; 5,309,046; 5,301,416; 5,294,975; 5,285,153; 5,280,203; 5,274,581; 5,272,368; 5,268,598; 5,260,611; 5,260,610; 5,258,668; 5,247,478; 5,247,477; 5,243,233; 5,241,224; 5,237,219; 5,220,533; 5,220,214; 5,200,920; 5,187,392; 5,166,604; 5,162,680; 5,144,167; 5,138,576; 5,128,565; 5,121,006; 5,111,423; 5,097,208; 5,091,661; 5,066,873; 5,045,772; 4,969,121; 4,930,107; 4,930,098; 4,930,097; 4,912,342; 4,903,223; 4,899,070; 4,899,067; 4,871,930; 4,864,161; 4,831,573; 4,785,423; 4,774,421; 4,713,792; 4,677,318; 4,617,479; 4,609,986; 4,020,469; and certain foreign patents. Copyright © 1996 Altera Corporation. All rights reserved. Printed on Recycled Paper. ...
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