CN10-pn fabrication - Fabrication of p-n junctions and...

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1 1 Fabrication of p-n junctions and devices in general 2 Outline P-n junctions and semiconductor devices Semiconductor devices and interconnects: fabrication issues Doping depth profile control during epitaxial growth via diffusion via ion implantation Insulation/dielectrics/oxide layers Contacts and metallization Lithography for layout control Summary
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2 3 Device Fabrication issues Devices (including their internal p-n junctions) front-end- processing and their interconnects back-end processing are created in a multistep process. Device and interconnect fabrication requires control of semiconductor material in multi-semiconductor devices doping profiles including junction location , that is where the transition from p to n-type carrier concentrations occurs electrical insulation layers (e.g., oxides) for current blocking within and among devices device contacts, metal and/or polysilicon “metallization” or metal layers for connecting devices (essentially wiring) 4 Control of the above normal to the plane of the wafer in the plane of the wafer during fabrication is achieved by what can be quite different respective approaches.
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