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ece253f_2004_exam - Print First Name Last Name Student...

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Unformatted text preview: Print: First Name: ............................. Last Name: ............................. . Student Number: ............................................... University of Toronto Examiner — Parham Aarabi Faculty of Applied Science and Engineering Final Examination — December 17, 2004 ECE253F — Digital and Computer Systems 1. There are 7 questions and 13 pages. Do all questions. The total number of marks is 150. The duration of the test is 2 hours 30 minutes. 2. ALL WORK IS TO BE DONE ON.THESE SHEETS! Use the back of the pages if you need more space. Be sure to indicate clearly if your work continues elsewhere. 3. Open book ~ Exam Type D. Only authorized photocopies of copyrighted material are allowed. A photocopy of Appendix A for Verilog is permitted. 4. All NON—PROGRAMMABLE calculators permitted. .5. Please put your final solution in the appropriate spaces. A big space does not necessarily mean a long answer is required. 6. Place your student card on your desk Page 1 of 13 1 [20] 3 [20] 6 [25] Total [150] l [20 marks] 1. [12 marks] We want to build a system using logic gates to compute the parity of an 11-bit number. The parity is defined as 1 if and only if there are an odd number of 1’s in the number. One way of doing this is to build the circuit 1 bit at a time (as in the ripple-carry adder), such that the circuit computes the parity one bit at a time. A block diagram of the first few bits of such a circuit is shown below where the input number is defined by the a; bits, and the final parity is defined as pg. 4 a) Using any logic gates you like, show how to implement the parity checking system one bit at a time. Page 2 of 13 [8 marks] b) Reduce the delay of the above circuit by implementing the parity check 2 bits at a time as shown below. ’ am ai pout pin Page 3 of 13 [20 marks] 2. Analyze the finite state machine shown below. Assume that all D flip-flops were initially cleared. - Clock [6 marks] a) Determine the logic expressions for next-state variables (D1 and D2) and the output (Z)- [7 marks] b) Draw the state transition table. [7 marks] 0) Draw the state diagram. Page 4 of 13 [20 marks] 3. Shipwrecked on a deserted island, you attempt to make your own radio from whatever is left of your ship. You get 1 antenna, 15 NMOS transistors (with delay lns), a solar panel that can supply a voltage of 5V, and plenty of resistors and wires. [4 marks] a) Design a circuit that can broadcast (using square waves) a continuous repetition of 1 ' following by 0 followed by 1 (i.e. 10101010 - - - with the duration of each 1 or 0 being 3ns). . [10 marks] b) Design a circuit that can broadcast the code 101000101000101000 - -- with the same du- \ ration per bit as in part a). [6 marks] 0) Are you sure the circuit in part b) does not send 010000010000010 - -- ? How can you make sure we send the 101000101000 - - - code? Page 5 of 13 n [25 marks] 4. Consider the following 68000 assembly program: ORG $10000 MOVEAL #$10000,A0 MOVEA.L #$20000,A1 MOVE #$FF,D0 BSR LOOP STUCK BRA STUCK LOOP MOVE (A0)+,(A1)+ SUB #1,D0 CMP #0,D0 BEQ NOMORE BSR LOOP NOMORE RTS [8 marks] a) Find the value of the ‘NOMORE’ address by finding the instruction size and hence the address of each instruction. Page 6 of 13 [10 marks] b) What are the contents of the stack (note, the stack is the part of the memory that is referenced by A7) when we first get to ‘NOMORE’? [7 marks] 0) Rewrite this code such that the same task is performed by fewer instructions. Page 7 of 13 it [20 marks] 5. You are giVen the following VerilOg code: module mystery(X,Clock,Reset); output [1:0]X; input Clock,Reset; reg [1:0]X; reg [1:O]S; reg [1:0]nextS; always @(posedge Clock) if (Reset) S<=1; else S=nextS; always @(nextS) case (S) 1: begin nextS=2; X21; end 2: begin nextS=3; X22; end 3: begin nextS=1; X=3; end endcase endmodule [10 marks] ‘ a) U'nf0rtunately, this code which describes a 1 to 3 counter, has three major, non—syntax, errors. Find all of the three NON—SYNTAX errOrs in the above Verilog code and fix them such that the code would describe the desired 1 to 3 counter. Make sure to explain exactly What the errors are and how the‘propoSed solutions resolve the problems. You can write your modifications / corrections directly on the above code. Page 8 of 13 [10 marks] b) Can this code be simplified in any way such that the number of lines required is lass but the functionality is the same? If so, go ahead and perform the simplification and draw the logic gate level representation of the logic circuit defined by your verilog code (feel free to use any logic gate as well as DFFs). Page 9 of 13 L [25 marks] 6. The performance of the 68000 processor is improved by using a state-of-the—art 3-D holo— [12 marks] graphic memory (HRAM) system. This 3—D memory requires a 4-bit row address, a 4-bit column address, and a 4-bit horizontal plane address. So, in total it contains 212 = 4096 bits of memory. For the purposes of this question, assume that this memory is extremely fast, such that you do not have to worry about any memory delays. The control signals for this HRAM are (aside from the address bits) ENABLE and BITOUT. When ENABLE is set to 1, the location specified by the 3-D address is first inverted (i.e. if it is 0, it is set to 1 and vice versa) and then read through BITOUT. Note that we can only read from the HRAM, and cannot directly write to it. a) Design the interface circuits to connect the HRAM to the 68000 processor, such that reading from each 68000 address starting from $FFF000 to $FFFFFF reads a single bit from the HRAM. (i.e. if the 68000 reads from location $FFF000 the first bit in HRAM is read, and if the 68000 reads from location $FFFFFF, the last location in HRAM is read.) Page 10 of 13 [13 marks] b) Since every memory bit read flips the contents of that memory location, you realize that data can actually be written to this HRAM. Write 68000 assembly code to copy 512 bytes from regular memory (starting from $010000 to $0101FF) to this memory. Page 11 of 13 [20 marks] 7. In this question, you will write a 68000 program to check whether a number stored in memory is prime. Note that you you may want to use the DIVU (divide unsigned) and MULU (multiply unsigned) instructions for this question. [8 marks] a) Write a 68000 subroutine to take a number in memory location N and to check to see if it is divisible by a number in memory location X. If it is, then the memory location RES should be set to a 1, otherwise, the location RES should be set to a 0. You can assume that N and X addresses of two 8—bit numbers that are already stored in memory. Also assume that N, X, and RES have been previously declared. Page 12 of 13 [12 marks] b) Write a 68000 assembly program to check if an 8-bit number in memory location N is prime (i.e. a number is prime if it is ONLY divisible by 1 and N and no other number in-between). Feel free to use your subroutine in part a). Page 13 of 13 ...
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