This preview shows pages 1–7. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: 3. (5 points) Problem 8.8 from the textbook. 4. (5 points) Describe in words how to decide the smallest clock period for a synchronous circuit. What is the hold time of a register? How does the hold time constrain the circuit delays for a synchronous circuit? Solution: The setup time of registers will constrain the minimum clock period, which is given by: T clock,min = T c2q + T logic, max +T setup . Hold time is the minimum amount of time the same data should be kept at the input of a register after the clock edge in order to ensure the proper operation of the register. To satisfy the hold time constraint, we need to have: T c2q + T logic, min > = T hold. Therefore, hold time imposes a lower bound for the delay of the combinational logic. 5. (5 points) Problem 9.2 (a) and (b) from the textbook. 6. (5 points) Problem 9.6 from the textbook....
View Full
Document
 Spring '08
 JiangHu

Click to edit the document details