454Fall07HW8_Solution

454Fall07HW8_Solution - 3. (5 points) Problem 8.8 from the...

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ECEN 454 Digital Integrated Circuit Design Fall 2007 Homework 8 Solutions 1. (5 points) Design a CMOS positive-edge triggered master-slave D flip-flop and a C 2 MOS (clocked CMOS) negative-edge triggered master-slave D flip-flop. Draw a complete transistor-level schematic for each of your design. Describe in words the working of your C 2 MOS D flip-flop. Solution: CMOS C 2 MOS For the C 2 MOS negative-edge triggered master-slave D-FF, It contains two D-latches. The first acts as the input switch, accepting the input signal when the clock is high. When the clock goes low, the second stage passes the state of D to Q while the first stage blocks further changes in D.
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2. (5 points) Problem 8.7 from the textbook. If taking the delay in the three-input AND gates into consideration, the waveform should look like above. Otherwise the Q remains its initial state all the time.
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Unformatted text preview: 3. (5 points) Problem 8.8 from the textbook. 4. (5 points) Describe in words how to decide the smallest clock period for a synchronous circuit. What is the hold time of a register? How does the hold time constrain the circuit delays for a synchronous circuit? Solution: The setup time of registers will constrain the minimum clock period, which is given by: T clock,min = T c2q + T logic, max +T setup . Hold time is the minimum amount of time the same data should be kept at the input of a register after the clock edge in order to ensure the proper operation of the register. To satisfy the hold time constraint, we need to have: T c2q + T logic, min > = T hold. Therefore, hold time imposes a lower bound for the delay of the combinational logic. 5. (5 points) Problem 9.2 (a) and (b) from the textbook. 6. (5 points) Problem 9.6 from the textbook....
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454Fall07HW8_Solution - 3. (5 points) Problem 8.8 from the...

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