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454Fall07HW8 - 3(5 points Problem 8.8 from the textbook 4(5...

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ECEN 454 Digital Integrated Circuit Design Fall 2007 Homework 8 Due on November 30, Friday 1. (5 points) Design a CMOS positive-edge triggered master-slave D flip-flop and a C 2 MOS (clocked CMOS) negative-edge triggered master-slave D flip-flop. Draw a complete transistor-level schematic for each of your design. Describe in words the working of your C 2 MOS D flip-flop. 2. (5 points) Problem 8.7 from the textbook.
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Unformatted text preview: 3. (5 points) Problem 8.8 from the textbook. 4. (5 points) Describe in words how to decide the smallest clock period for a synchronous circuit. What is the hold time of a register? How does the hold time constrain the circuit delays for a synchronous circuit? 5. (5 points) Problem 9.2 (a) and (b) from the textbook. 6. (5 points) Problem 9.6 from the textbook....
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