454Fall07HW7 - transistors. (b). Size your transistors such...

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ECEN 454 Digital Integrated Circuit Design Fall 2007 Homework 7 Due on November 19, Monday 1. (5 points) Problem 7.1 (a) from the textbook. You should identify the circuit in the layout and draw the schematic. 2. (5 points) Problem 7.7 from the textbook. You only need to do the hand calculation. For this problem, you can assume the two inputs are tied together. 3. (5 points) Problem 7.12 from the textbook. 4. (5 points) Problem 8.6 from the textbook. 5. (5 points) (a). Determine the function F in the following circuits. a) b) (b). Use AOI (and-or-invert) gate(s) to implement the same function in b). 6. (5 points) (a). Draw the schematic of a CMOS circuit implementing the logic function ) )( ( EG EF D BC A F + + + = . You should try to use a minimum number of
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Unformatted text preview: transistors. (b). Size your transistors such that the circuit has the same worst case rise and fall times. You can assume that the minimum channel length is used for both N and P mos transistors, which is the same for both types of transistors. In addition, the mobility of holes is half of that of electrons and other relevant device parameters are the same for N and P type transistors. Notice that in addition to having the balanced worst case rise and fall times, you should also try to balance the signal delays between different conducting paths in your circuit so as to minimize the chip area. (c). Draw the schematic of the pseudo-NMOS version of your design....
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This note was uploaded on 04/17/2008 for the course ELEN 454 taught by Professor Jianghu during the Spring '08 term at Texas A&M.

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