454Spring08HW3_Solution

# 454Spring08HW3_Solution - Solution V s =5V V D =3V V G 2(5...

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ECEN 454 Digital Integrated Circuit Design Spring 2008 Homework 3 Solution 1. (5 points) A PMOS transistor is biased as shown in the following figure. The threshold voltage is -2V. Draw an I-V plot (drain current vs. gate voltage) for the PMOS transistor as the gate voltage is varied from 5V to 0V. The reference direction for the drain current is from drain to source. You do not have to be precise in terms of absolute numbers, but you need to properly label all the break points along the x-axis where the PMOS transistor starts to a new region of operation and label all the regions of operations that will be encountered.

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Unformatted text preview: Solution: V s =5V V D =3V V G 2. (5 points) Problem 3.13 of the textbook. 3. (5 points) Problem 3.16 of the textbook. 4. (5 points) For problem 3.17 of the textbook, a. Complete 3.17 (b). b. For the same NMOS transistor, compute the total C GS , C GB , C GD and C GG for different regions of operation. You can assume there is no gate-bulk overlap capacitance. Notice that you should include all the capacitance components. Solution: (a) Gate-Drain overlap capacitance: C GD = C ox *L D *W = ( ε ox / t ox )*L D *W = (3.9 * ε )*L D *W = 4.314fF (b)...
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454Spring08HW3_Solution - Solution V s =5V V D =3V V G 2(5...

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