454Fall07HW6

454Fall07HW6 - ECEN 454 Digital Integrated Circuit Design...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
ECEN 454 Digital Integrated Circuit Design Fall 2007 Homework 6 Due on November 2, Friday 1. (5 points) Consider the following inverter chain design problem. The unit-sized (1X) inverter has an input capacitance of C 1 . The load capacitance at the end of the chain is C L = 140C 1 . The first inverter’s size is fixed at 1X (decided by the upstream logic). The intrinsic capacitances (drain caps) at the output node of each inverter are neglected . Determine the optimum number of inverter stages and the optimum sizing for each inverter based on equivalent RC delay models. What is your optimum propagation delay for the whole chain assuming that a 1X inverter has an equivalent resistance of R 0 ? 2. (5 points) Compute the Elmore delays at node 1, 5 and 6 in the RC tree. C 1 1? ? 1x inverter C L = 140C 1 R4 C4 R1 R2 R3 C1 C2 C3 R5 C6 C5 R6 1 6 5
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
3. (5 points)
Background image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 04/17/2008 for the course ELEN 454 taught by Professor Jianghu during the Spring '08 term at Texas A&M.

Page1 / 2

454Fall07HW6 - ECEN 454 Digital Integrated Circuit Design...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online