454Fall07HW3

# 454Fall07HW3 - operation and label all the regions of...

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ECEN 454 Digital Integrated Circuit Design Fall 2007 Homework 3 Due on September 26, Wednesday 1. (5 points) A PMOS transistor is biased as shown in the following figure. The threshold voltage is -2V. Draw an I-V plot (drain current vs. gate voltage) for the PMOS transistor as the gate voltage is varied from 5V to 0V. The reference direction for the drain current is from drain to source. You do not have to be precise in terms of absolute numbers, but you need to properly label all the break points along the x-axis where the PMOS transistor starts to a new region of
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Unformatted text preview: operation and label all the regions of operations that will be encountered. 2. (5 points) Problem 3.7 of the textbook. 3. (5 points) Problem 3.8 of the textbook. 4. (5 points) For problem 3.17 of the textbook, a. Complete 3.17 (b). b. For the same NMOS transistor, compute the total C GS , C GB , C GD and C GG for different regions of operation. You can assume there is no gate-bulk overlap capacitance. Notice that you should include all the capacitance components. V s =5V V D =3V V G...
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## This note was uploaded on 04/17/2008 for the course ELEN 454 taught by Professor Jianghu during the Spring '08 term at Texas A&M.

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