ch9 - STANDARD COMBINATIONAL MODULES 1 Decoders Encoders...

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Unformatted text preview: STANDARD COMBINATIONAL MODULES 1 Decoders Encoders Multiplexers (Selectors) Demultiplexers (Distributors) Shifters Introduction to Digital Systems 9 { Standard Combinational Modules Binary decoders High-level description: Inputs: x = (x ;1 : : : x0) x Enable E 2 f0 1g Outputs: y = (y2n;1 : : : y0) y n 2 j 2 f0 1g 2 f0 1g i 1 Function: y = 0 i 8 > < > : if (x = i) and otherwise n j (E = 1) x= and ; X1 x2 =0 j n j i = 0 ::: 2 ;1 Introduction to Digital Systems 9 { Standard Combinational Modules 3 E En y 0 0 1 2 n-Input Binary Decoder y 1 2 x y x 1 1 x n-1 n-1 2 -1 Figure 9.1: n-input n y n 2 -1 binary decoder. 9 { Standard Combinational Modules Introduction to Digital Systems Outputs 0 0 Inputs Example 9.1: 3-input binary decoder 4 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 Binary speci cation: Inputs: E x2 x1 x0 x y7 y6 y5 y4 y3 y2 y1 y0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 j 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 x = (x ;1 : : : x0) x E 2 f0 1g Outputs: y = (y2 ;1 : : : y0) y n 2 f0 1g 2 f0 1g n n i Function: y = E m (x) i i i = 0 ::: 2 ;1 Introduction to Digital Systems 9 { Standard Combinational Modules Example 9.2: Implementation of 2-input decoder 5 y0 = x01x00E y1 = x01x0E y2 = x1x00E y3 = x1x0E E y0 x0 x1 y1 y2 y3 Figure 9.2: Gate network implementation of a 2-input binary decoder. Introduction to Digital Systems 9 { Standard Combinational Modules Decoder uses 6 OPCODE field Instruction Other fields E=1 4-Input Binary En Decoder 15 . . . 4 3 2 1 0 LOAD STORE ADD JUMP Figure 9.3: Decoded operations Operation decoding. Introduction to Digital Systems 9 { Standard Combinational Modules Decoder uses 7 Cell referenced when address is Data input 00000000000010 Data input Binary cell E=1 Address 14 RAM Module (2 14 x 1) Address 14 Binary Decoder 0 1 2 16383 Read/write Read/write Data output (a) (b) Data output Figure 9.4: Random-access memory (RAM): a) module b) addressing of binary cells. Introduction to Digital Systems 9 { Standard Combinational Modules Binary decoder and or gate universal set Example 9.5: 8 x2x1x0 z2 z1 z0 000 001 010 011 100 101 110 111 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 1 0 0 Introduction to Digital Systems 9 { Standard Combinational Modules 9 (y7 : : : z2(x2 x1 z1(x2 x1 z0(x2 x1 E=1 En y0 ) x0 ) x0 ) x0 ) 0 1 = = = = dec(x2 x1 x0 1) y1 y5 y7 y0 y3 y2 y4 y5 y0 y 1 2 3 Binary Decoder y 2 3 z2 x 0 0 1 2 y x1 x2 y4 4 5 z 1 y 5 6 7 y 6 7 z0 y Figure 9.5: Network in Example 9.5 Introduction to Digital Systems 9 { Standard Combinational Modules Decoder networks: Coincident decoding 10 x = (xleft xright) xleft = (x7 x6 x5 x4) xright = (x3 x2 x1 x0) x = 24 xleft + xright y = DEC (xleft) w = DEC (xright) z = AND(y w ) i s t i = 24 s + t Introduction to Digital Systems 9 { Standard Combinational Modules 11 x3 x2 x1 x0 0 1 1 0 0 4-Input Binary En Decoder 15 . . .4 3 2 1 0 w 4 1 z0 4-Input Binary Decoder 2 1 0 x4 x5 x6 x7 0 1 0 0 y 2 ... 1 z 36 En 15 1 E z 255 Figure 9.6: 8-input coincident decoder. 9 { Standard Combinational Modules Introduction to Digital Systems n-input coincident decoder 12 y = dec(xleft E ) w = dec(xright 1) z = (and(y2 n=2 ;1 w2 n=2 ;1) : : : and(y w ) : : : and(y0 w0)) s t Introduction to Digital Systems 9 { Standard Combinational Modules 13 x0 x n/2-1 1 En DECODER W w n/2 2 -1 wt w0 z0 y0 x n/2 x n-1 DECODER Y ys En y n/2 2 -1 E z n/2 2 s+t z n 2 -1 Figure 9.7: n-input coincident decoder. Introduction to Digital Systems 9 { Standard Combinational Modules Tree decoding 14 x = (xleft xright) xleft = (x3 x2) xright = (x1 x0) Introduction to Digital Systems 9 { Standard Combinational Modules 4-input tree decoder x3 x=6: 0 1 15 x2 1 0 DEC x1 1 0 x0 Level 1 E En 3 2 1 0 0 0 1 0 1 0 DEC 3 En 1 0 DEC 2 En 1 0 DEC 1 En 1 0 DEC 0 En Level 2 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 0 z 15 0 0 0 z 12 0 0 0 0 z8 0 1 z 6 =1 0 0 z4 0 0 0 0 z0 Figure 9.8: 4-input tree decoder. Introduction to Digital Systems 9 { Standard Combinational Modules n-input tree decoder 16 w = dec(xleft E ) z = (dec(xright w2 n=2 ;1 ) : : : dec(xright w ) : : : dec(xright w0)) t Introduction to Digital Systems 9 { Standard Combinational Modules 17 x x n-1 left x n/2 x right x0 x n/2-1 Level 1 E En DEC w n/2 2 -1 wt w0 En En DEC t DEC 0 En Level 2 DEC 2 -1 n/2 z n 2 -1 z 2 (n/2)t+s z0 Figure 9.9: n-input two-level tree decoder. Introduction to Digital Systems 9 { Standard Combinational Modules Comparison of decoder networks 18 Decoder modules and gates Load per network input Fanout per decoder output Number of module inputs (related to number of connections) Delay Coincident 2 22 Tree k k 2 +1 { k k k k 1 decoder input 2 decoder inputs (max) 2 and inputs 1 enable input 2k + 2 + 22 +1 1 + k + 2 + k2 k tdecoder + tAND 2tdecoder Introduction to Digital Systems 9 { Standard Combinational Modules Example 9.6: 6-input decoder E 19 Decoder x0 x1 x2 0 1 7 z0 z1 E x1 x2 0 1 7 Decoder x0 0 1 7 z0 z1 z7 1 x4 x5 0 1 7 (a) Figure 9.10: Decoder x3 x4 x5 Decoder x3 z 63 Decoder 0 1 7 z 56 z 57 z 63 (b) Implementation of 6-input decoder. a) Coincident decoder. b) Tree decoder. Introduction to Digital Systems 9 { Standard Combinational Modules Example 9.6 (cont.) 20 Coincident Decoder modules 2 and gates 64 Load per network input 1 decoder input Fanout per decoder output 8 and inputs Number of module inputs 136 3d Delay Tree 9 { 8 decoder inputs (max) 1 enable input 36 4d Introduction to Digital Systems 9 { Standard Combinational Modules 21 Decoder Cell array Binary cell Data input E=1 0 1 2 0 1 2 12 Address Tree Decoder 4095 4096 lines from decoder to cell array Read/write 4095 Data output (a) Figure 9.11: a) System with tree decoder. 9 { Standard Combinational Modules Introduction to Digital Systems 22 Decoder E=1 Cell array 0 0 Data input 6 Binary Decoder 63 1 12 Address E=1 6 Binary Decoder 0 63 4095 Read/write 128 lines from decoder to cell array equivalent to coincident decoder (b) Modified binary cell Data output Figure 9.11: b) System with coincident decoder. Introduction to Digital Systems 9 { Standard Combinational Modules Binary encoders E En 23 x x 0 1 0 1 -Input Binary Encoder y 0 1 0 1 y n-1 n-1 x n 2 -1 n 2 -1 Ac A Figure 9.12: 2n -input Introduction to Digital Systems 2 n binary encoder. Outputs 9 { Standard Combinational Modules Inputs y Binary encoder: high-level speci cation 24 x = (x2 ;1 : : : x0) x 2 f0 1g, with at most one x = 1 E 2 f0 1g Outputs: y = (y ;1 : : : y0) y 2 f0 1g A 2 f 0 1g Inputs: n i i n j Function: y = i if (x = 1) and (E = 1) 0 otherwise i A= 1 0 8 > < > : 8 > < > : if (some xi = 1) and otherwise (E = 1) y= and n j ; X1 y2 =0 j n j i = 0 ::: 2 ;1 9 { Standard Combinational Modules Introduction to Digital Systems Example 9.7: Function of an 8-input binary encoder 25 E x7 x6 x5 x4 x3 x2 x1 x0 y y2 y1 y0 A 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 0 0 Introduction to Digital Systems 9 { Standard Combinational Modules Binary speci cation of encoder 26 Inputs: x = (x2 ;1 : : : x0) x n i 2 f0 1g, with at most one x = 1 i E 2 f0 1g Outputs: y = (y ;1 : : : y0) y n j 2 f0 1g A 2 f 0 1g Function: y = E P(x ) j = 0 : : : n ; 1 j k A = E P(x ) i = 0 : : : 2 i n ;1 Introduction to Digital Systems 9 { Standard Combinational Modules Example 9.8 27 y0 = E (x1 x3 x5 x7) y1 = E (x2 x3 x6 x7) y2 = E (x4 x5 x6 x7) A = E (x0 x1 x2 x3 x4 x5 x6 x7) Introduction to Digital Systems 9 { Standard Combinational Modules 28 x7 x6 x5 x4 x3 x2 x1 x0 E y0 y1 y2 A Figure 9.13: Implementation of an 8-input binary encoder. Introduction to Digital Systems 9 { Standard Combinational Modules Uses of binary encoders 29 Wind direction in unary code 0 1 0 n nw w sw s se ne e 0 0 0 0 2 3 4 5 BINARY ENCODER 1 Wind direction in binary code 0 1 2 1 0 0 0 0 6 7 Figure 9.14: Wind direction encoder. Introduction to Digital Systems 9 { Standard Combinational Modules Priority encoders: High-level description Inputs: x = (x2n;1 : : : x0) x 2 f0 1g Outputs: y = (y ;1 : : : y0) y 2 f0 1g i n j 30 Function: y= i 0 A= 1 0 8 > < > : 8 > < > : if (xi = 1) and otherwise (x = 0 k > i) and (E = 1) k if (some xi = 1) and otherwise (E = 1) y= and n j ; X1 y2 =0 j j i k 2 f0 1 : : : 2 n ; 1g 9 { Standard Combinational Modules Introduction to Digital Systems 8-input priority encoder 31 E x7 x6 x5 x4 x3 x2 x1 x0 y2 y1 y0 A 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 0 0 Introduction to Digital Systems 9 { Standard Combinational Modules 32 E Lowest priority z 0 0 En 0 1 x x 0 1 Priority Resolution z 1 1 1 -Input Binary Encoder 0 y 0 1 0 1 y n-1 n-1 x n 2 -1 Highest priority 2 -1 n 2 -1 n 2 -1 n 2 -1 Ac A Figure 9.15: Priority encoder. Introduction to Digital Systems 2 z n n 9 { Standard Combinational Modules Outputs Inputs y Priority resolution: high-level and binary-level description Inputs: x = (x2n;1 : : : x0) x 2 f0 1g Outputs: z = (z2n;1 : : : z0) z 2 f0 1g i i 33 Function: z = 1 if (x = 1) and (x = 0 k > i) 0 otherwise with i k = 0 1 : : : 2 ; 1 Binary description: i i k n 8 > < > : z = x02 ;1x02 ;2 : : : x0 +1x i n n i i i = 0 1 ::: 2 i i n ;1 c ;1 = c x z = c0 x i i i i Introduction to Digital Systems 9 { Standard Combinational Modules 34 x0 c0 x0 x1 x2 z0 z1 z2 x2 x3 z3 x3 (a) Figure 9.16: z0 Cell x1 c1 z1 c2 z2 z3 (b) 4-bit priority resolution networks: a) parallel b) iterative. Introduction to Digital Systems 9 { Standard Combinational Modules Uses of priority encoders Request lines E=1 35 Device A 1 lowest priority 0 En Highest priority 0 request Device B 0 PRIORITY ENCODER 1 0 PROCESSOR 1 1 Device C 1 2 Device D 0 highest priority 3 Ac A=1 Request present Figure 9.17: Resolving interrupt requests using a priority encoder. Introduction to Digital Systems 9 { Standard Combinational Modules 36 x 7 x 6 x 5 x 4 x 3 x2 x1 x 0 0 0 1 0 1 0 0 1 E=1 En PRIORITY ENCODER Ac 0 1 2 1 0 1 SHIFTER 1 0 1 0 0 1 0 0 (x shifted left 2 positions with 0s inserted into vacated positions) Figure 9.18: Detecting the leftmost 1 in a bit-vector and removing leading zeroes. Introduction to Digital Systems 9 { Standard Combinational Modules Multiplexers (selectors) High-level and binary-level description Inputs: x = (x2n;1 : : : x0) x 2 f0 1g 2 f0 1g i 37 s = (s ;1 : : : s0) s E 2 f0 1g Outputs: z 2 f0 1g n j Function: z = x if E = 1 0 if E = 0 s 8 > < > : s= z=E i n j ; X1 s2 =0 j i j 2 n ; 62 X 1 4 x m (s) =0 i 3 7 5 Introduction to Digital Systems 9 { Standard Combinational Modules 38 E x0 x1 0 1 2 En x2 2 - Input Multiplexer Data inputs Data output z x n 2 -1 n 2 -1 n-1 n 0 s n-1 s0 Select inputs Figure 9.19: 2n -input multiplexer. Introduction to Digital Systems 9 { Standard Combinational Modules Example 9.11: 4-input multiplexer 39 E s1 s0 z 1 0 0 x0 1 0 1 x1 1 1 0 x2 1 1 1 x3 0 - - 0 z = E (x0m0(s1 s0) x1m1(s1 s0) x2m2(s1 s0) x3m3(s1 s0)) = E (x0s01s00 x1s01s0 x2s1s00 x3s1s0) Introduction to Digital Systems 9 { Standard Combinational Modules 40 x0 x1 x 2 z x3 E s1 s0 Figure 9.20: Gate implementation of 4-input multiplexer Introduction to Digital Systems 9 { Standard Combinational Modules Typical uses R0 R1 R0 R2 R3 R4 41 SelA 0 1 0 1 2 3 MUX A MUX B SelB A B For n-bit operands, Mux A and MuxB replicated n times and connected to the corresponding bit s of the input vectors. f FUNCTIONAL UNIT Example: SelA = 1, SelB = 2 Z = f(R1,R3) Z= f(A,B) Figure 9.21: Multiplexer: example of use. Introduction to Digital Systems 9 { Standard Combinational Modules Multiplexer as universal combinational module 42 connect input variables x to select inputs of multiplexer s set data inputs to multiplexer equal to values of function for corresponding assignment of select variables using a variable at data inputs reduces size of the multiplexer Introduction to Digital Systems 9 { Standard Combinational Modules Example 43 E (x2 x1 x0) = X m(1 2 4 6 7) = x02(x01x0) x02(x1x00) x2(x01x00) x2(x1x00) x2(x1x0) = x02m1(x1 x0) x02m2(x1 x0) x2m0(x1 x0) x2m2(x1 x0) x2m3(x1 x0) = x2m0(x1 x0) x02m1(x1 x0) 1 m2(x1 x0) x2m3(x1 x0) Introduction to Digital Systems 9 { Standard Combinational Modules 44 E=1 En 0 1 1 0 1 0 1 1 0 1 2 3 4 5 6 7 E=1 En 8 - Input Multiplexer x f = one-set(1,2,4,6,7) x' 1 x 2 1 2 3 4 - Input Multiplexer 2 0 f = one-set(1,2,4,6,7) 2 1 2 1 0 x x 2 Select inputs 1 0 x 0 x 1 x 0 (c) (a) x0 x0 0 x2 1 0 1 x2 x' 2 x2 1 1 0 1 x1 1 x1 (b) Figure 9.22: Implementation of f (x2 x1 x0) = one-set (1,2,4,6,7): a) 8-input multiplexer b) K-map c) 4-input multiplexer. 9 { Standard Combinational Modules Introduction to Digital Systems Example 9.12: One-bit adder Inputs: a b c Outputs: z c 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 in in out 45 2 f0 1g 2 f0 1g out a b c z c 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 z = (a0 b0) c (a0b) c0 (ab0) c0 (ab) c = c m0(a b) c0 m1(a b) c0 m2(a b) c m3(a b) c = 0 m0(a b) c m1(a b) c m2(a b) 1 m3(a b) in in in in in in in in out in in Introduction to Digital Systems 9 { Standard Combinational Modules 46 E=1 E=1 cin c'in 0 1 2 3 En 4-Input Multiplexer 0 0 1 En 4-Input Multiplexer z 2 cout 1 0 3 1 a b 1 0 z: cin cout : cin 0 a 1 0 0 1 b 1 0 a 0 0 0 1 1 1 b 0 1 1 cin a c'in c'in cin b a 0 cin cin 1 b Figure 9.23: Implementation of one-bit adder with 4-input multiplexers. 9 { Standard Combinational Modules Introduction to Digital Systems Multiplexer trees 47 sleft = (s3 s2) sright = (s1 s0) w = x(4 + j j sright ) sleft 0 j 3 z=w z = x4 s = 4sleft + sright sleft +sright =x s Introduction to Digital Systems 9 { Standard Combinational Modules 16-input tree multiplexer 48 x 15 x 14 x 13 x 12 3 2 1 0 x 11 x 10 x 9 x 8 3 2 1 0 x7 3 x6 2 x5 x4 1 0 x3 x2 x1 x0 1 En 1 0 1 En 1 0 1 En 1 0 1 En 1 0 3 2 1 0 MUX MUX MUX MUX s1 s0 0 1 x 13 x9 x5 x1 s3 s2 E 1 0 En 1 0 3 2 1 0 MUX z = x9 Figure 9.24: Tree implementation of a 16-input multiplexer. Introduction to Digital Systems 9 { Standard Combinational Modules Demultiplexers (distributors) A high-level description: Inputs: x E Outputs: 49 2 f0 1g s = (sn;1 : : : s0) y = (y2n;1 : : : y0) i s 2 f0 1g y 2 f0 1g j i ( Function: y = x if (i = s) andE E = 1) 0 if (i 6= s) or ( = 0) 8 > < > : s= n j ; X1 s2 0 i 2 =0 j j n ;1 Introduction to Digital Systems 9 { Standard Combinational Modules 50 E En 0 1 y0 y 1 2 y Demultiplexer (DMUX) 2 Data input x Data outputs 2 -1 n-1 0 n y n 2 -1 s n-1 s0 Select inputs Figure 9.25: 2n -output demultiplexer. Introduction to Digital Systems 9 { Standard Combinational Modules Example 9.13: 4-output demultiplexer 51 E s1 s0 s y3 y2 y1 y0 1 0 0 0 0 0 0 x 1 0 1 1 0 0 x 0 1 1 0 2 0 x 0 0 1 1 1 3 x 0 0 0 0 - - - 0 0 0 0 y = E x m (s) i i 0 i 2 n ;1 Introduction to Digital Systems 9 { Standard Combinational Modules 52 E x y y 0 1 y2 y3 s 1 s 0 Figure 9.26: Gate network implementation of a 4-output demultiplexer. 9 { Standard Combinational Modules Introduction to Digital Systems 53 Y DMUX 0 1 2 3 Sel S0 S1 S2 S3 0 1 2 3 MUX X For n-bit operands, Mux and Dmux replicated n times and connected to the corresponding bit s of the input/output vectors. f FUNCTIONAL UNIT Z= f(X) Figure 9.27: Demultiplexer: example of use. 9 { Standard Combinational Modules Introduction to Digital Systems x n x n-1 xi x 0 x -1 n n-1 i 0 -1 E s shift/ no shift n-bit Simple Shifter d n-1 i 0 left/ right Introduction to Digital Systems y n-1 yi (a) Figure 9.28: n-bit y0 xn x n-1 x i+1 x 1 x 0 x -1 s= YES d= RIGHT shift/ no shift left/ right Simple Shifter E=1 y n-1 yi (b) y0 simple shifter: a) block diagram b) right shift c) left shift. s= YES d= LEFT shift/ no shift left/ right x n x n-1 x n-2 x i-1 x 0 x -1 E=1 9 { Standard Combinational Modules y n-1 yi (c) y0 54 Simple shifter: High-level description Inputs: 55 x = (x x ;1 : : : x0 x;1) x 2 f0 1g d 2 fRIGHT LEFT g s 2 fY ES NOg E 2 f0 1g Outputs: y = (y ;1 : : : y0) y 2 f0 1g n n j n j Function: x ;1 y = x +1 x 0 i i i i 8 > > > > > < > > > > > : (d = LEFT ) and (s = Y ES ) and (E = 1) (d = RIGHT ) and (s = Y ES ) and (E = 1) (s = NO) and (E = 1) (E = 0) for 0 i n ; 1. 8 >0 > left shift with 0 insert > < x;1 = > 1 left shift with 1 insert > >x : ;1 left rotate 8 > 0 right shift with 0 insert > > x = < 1 right shift with 1 insert > > > x right rotate : 0 if if if if n n Introduction to Digital Systems 9 { Standard Combinational Modules Example 9.14: 4-input shifter 56 1 0 No shift no { 0 1 Right shift yes right Left shift yes left 0 Coding: s Control d x4 x3 x2 x1 x0 x;1 0 0 0 1 1 1 0 1 1 0 1 1 0 Data y3 y2 y1 y0 0 no 1 yes s d 0 right 1 left Introduction to Digital Systems 9 { Standard Combinational Modules 57 xn d LEFT RIGHT x n-1 x n-2 x1 x0 x -1 E s NO SHIFT y n-1 (a) xn x n-1 x n-2 x1 y0 x0 x -1 E En 3 1 0 2 1 0 En 3 1 0 2 1 0 MUX MUX s d y n-1 (b) Figure 9.29: y0 Implementation of a simple shifter: a) with gates b) with multiplexers. 9 { Standard Combinational Modules Introduction to Digital Systems p-shifter: High-level description x = (x + ;1 : : : x x ;1 : : : x0 x;1 : : : x; ) s 2 f0 1 ::: pg d 2 fLEFT RIGHT g E 2 f0 1 g Outputs: y = (y ;1 : : : y0) y 2 f0 1g Inputs: n p n n p n j 58 x j 2 f0 1g Function: x; y = x+ 0 i i i 8 > > > < > > > : s s if if if (d = LEFT ) and (E = 1) (d = RIGHT ) and (E = 1) (E = 0) 0 i n;1 Introduction to Digital Systems 9 { Standard Combinational Modules p-shifter x n+p-1 x n x n-1 x 0 x -1 x -p 59 s log(p+1) distance n-bit p-Shifter left/right En E d y n-1 y0 Figure 9.30: n-bit p-shifter. Introduction to Digital Systems 9 { Standard Combinational Modules Barrel shifter Stage 0 Stage 1 Stage 2 Stage 3 60 n+2p 0 or 4 SHIFT 0 or 8 SHIFT 0 or 1 SHIFT 0 or 2 SHIFT x d s0 1 Figure 9.31: Barrel shifter for p = 15. Introduction to Digital Systems 9 { Standard Combinational Modules s3 s2 s y Unidirectional shifters 61 x6 x5 x4 x3 x2 x1 x0 E En 3 1 0 2 1 0 En 3 1 0 2 1 0 En 3 1 0 2 1 0 En 3 1 0 2 1 0 MUX MUX MUX MUX s1 s0 y3 y2 y1 y0 Figure 9.32: Multiplexer implementation of a 4-bit right 3-shifter. Introduction to Digital Systems 9 { Standard Combinational Modules Typical uses of shifters 62 Alignment of a bit-vector Removal of the leading (or trailing) bits of a vector Performing multiplication or division by a power of two Extracting a subvector from a bit-vector, using a shifter instead of a selector Introduction to Digital Systems 9 { Standard Combinational Modules ...
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This note was uploaded on 04/14/2008 for the course CS M51A taught by Professor Ercegovac during the Fall '07 term at UCLA.

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