ch3 - COMBINATIONAL ICs Representation of binary variables...

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Unformatted text preview: COMBINATIONAL ICs Representation of binary variables at the physical level. Basic switch structure of gates and their operation. Realization of gates using cmos circuits. 1 Characteristics of circuits: load factors and fanout factors, propagation delays, transition times, and e ect of load. Three-state gates (drivers) and buses. Noise and noise margins. Evolution of ICs. VLSI circuit-level design styles. Packaging levels: chips, boards and cabinets. Introduction to Digital Systems 3 { Combinational ICs Representation of Binary Variables 2 representation of 0 and 1 by the values of electrical signals (voltages, currents, or electrical charges) and desired switching functions. realization of circuits that operate on these signals to implement the Typical values for a 3.3V cmos technology are VHmax 3.3V VLmax 0.8V VHmin 2.0V VLmin 0.0V Introduction to Digital Systems 3 { Combinational ICs Voltage regions 3 voltage V Hmax VHmin VLmax V H region Forbidden region V region V Lmin L Figure 3.1: Voltage regions. Introduction to Digital Systems 3 { Combinational ICs Positive and negative logic 4 x f y z Positive logic VH ! 1 VL ! 0 Negative logic VH ! 0 VL ! 1 Input Output Positive Negative voltages voltage logic logic x VL VL VH VH y VL VH VL VH z VL VL VL VH xy z xy z 0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 f = and f = or 1 1 1 0 Introduction to Digital Systems 3 { Combinational ICs Structure and operation of gates Switch and mos transistors 5 n-type: open (off) if VCA < VTn closed (on) if VCA > VTn VTn { the threshold voltage for n-type switch p-type: open (off) if VBC < VTp closed (on) if VBC > VTp VTp { the threshold voltage for p-type switch Introduction to Digital Systems 3 { Combinational ICs 6 V CA V Tn n-type switch Resistance between A and B very low: switch CLOSED (on) Resistance between A and B very high: switch OPEN (off) B C + VBC V Tp p-type switch Resistance between A and B very low: switch CLOSED (on) Resistance between A and B very high: switch OPEN (off) + B pS A nS C (a) V BC - V CA A logical symbol B C A NMOS transistor B C gate A drain source PMOS transistor B source C gate A (b) logical symbol B C drain A Figure 3.3: a) n-type and p-type controlled switches. b) nmos and pmos transistors. Introduction to Digital Systems 3 { Combinational ICs CMOS NOT gate Complementary MOS circuit VDD B pS 7 VDD vout VDD pS closed nS open pS open nS closed x vin C nS z A x z vout VDD vout vin Ground (0V) (a) vin v out VH VL VL VH (c) x VTn z 0 1 vin V - VTp DD (b) x z 1 0 (d) Figure 3.4: Circuit, I/O characteristic, and symbol Introduction to Digital Systems 3 { Combinational ICs Operation of not gate 8 VBC = VDD ; vin (VDD = VBC + vin) 1. vin < VTn =) VCA < VTn =) n-switch open If VDD > VTn + VTp then VBC > VTp =) p-switch closed and vout = VDD 2. vin > VDD ; VTp =) VBC < VTp =) p-switch is open If VDD > VTn + VTp then VCA > VTn =) n-switch is closed and vout = 0 Circuit operates as not if VLmax < VTn VH min > VDD ; VTp VDD > VTn + VTp 3 { Combinational ICs Introduction to Digital Systems NAND and NOR gates Circuit 1: NAND x y V DD 9 Circuit 2: NOR z x y V DD z x z x y z y Figure 3.5: Circuits for NAND and NOR gates. Introduction to Digital Systems 3 { Combinational ICs NAND and NOR gates (cont.) 10 xy 0 0 1 1 Circuit 1 Circuit 2 0 1 0 1 z 1 1 1 0 z 1 0 0 0 Introduction to Digital Systems 3 { Combinational ICs AND and OR gates AND x y V DD 11 OR z x y V DD z S3 S4 S5 z x y S4 S3 S5 z x S2 S6 S1 S2 S6 y S1 Figure 3.6: Circuits for and and or gates. Introduction to Digital Systems 3 { Combinational ICs Complex gates AND-OR-INVERT (AOI) u v z x y z = (uv + xy)' Figure 3.7: Complex gates. 12 OR-AND-INVERT (OAI) u v z x y z = [(u+v)(x+y)]' Introduction to Digital Systems 3 { Combinational ICs 13 u V DD v x y V DD V DD u v x y V DD S4 S5 S3 S6 z z S2 S7 S1 S8 Figure 3.7: Examples of complex gates. Introduction to Digital Systems 3 { Combinational ICs Transmission gate 14 C' x z C 0 1 n-switch p-switch off off on on Z - high impedance state z Z x C (a) Figure 3.8: a) Transmission gate Introduction to Digital Systems 3 { Combinational ICs XOR with transmission gates 15 x TG1 z TG2 y (b) Figure 3.8: b) xor gate x y z y TG1 TG2 z 0 on off x 1 off on x Introduction to Digital Systems 0 3 { Combinational ICs MUX with transmission gates 16 x0 TG1 x1 1 z x1 s (c) Figure 3.8: c) 2-input mux. MUX x0 0 z TG2 s z = mux(x1 x0 s) = x1s x0s 0 s TG1 TG2 z 0 on off x0 1 off on x1 3 { Combinational ICs Introduction to Digital Systems Timing parameters Input Output 17 high Input low 50% 50% high Output low high-to-low propagation delay low-to-high propagation delay 50% 50% t pHL t pLH (a) t high 90% low rise time 10% t r 90% 10% tf (b) fall time t Figure 3.9: a) Propagation delay. b) Rise and fall times. Introduction to Digital Systems 3 { Combinational ICs E ect of load a b c Gate 1 Gate 2 Gate 4 18 z d a Gate 3 Figure 3.10: A gate network i in Gate v in C in R in Figure 3.11: Equivalent circuit for gate input. Introduction to Digital Systems 3 { Combinational ICs E ect of load on propagation delay 19 high Input voltage low Load A high Output voltage low Load B Load B > Load A t t pLH (for load A) pLH (for load B) Figure 3.12: E ect of load on propagation delay. Introduction to Digital Systems 3 { Combinational ICs Load factor and total load 20 (Driving gate) Gate 1 Load factor: 1 Gate 2 3 Gate 3 Gate 4 2 Gate 5 Total load: 7 1 Figure 3.13: Output load of Gate 1. Introduction to Digital Systems 3 { Combinational ICs Voltage variations and noise margins Output levels Noise margins VHmin (OUT) Input levels 21 VHmin (IN) Forbidden region VLmax (OUT) VLmax (IN) Figure 3.14: Noise margins. Introduction to Digital Systems 3 { Combinational ICs Noise margins: Example 22 Levels High VH min(out) VH min(in) Low VLmax(out) VLmax(in) Noise margin 2.4 V 0.4 V 2.0 V 0.4 V 0.4 V 0.8 V Introduction to Digital Systems 3 { Combinational ICs Connecting modules to a bus s0 23 Module M0 a0 s1 y Module M1 a1 (bus line) sk Module Mk ak Figure 3.15: Gate network for selecting a module output. Introduction to Digital Systems 3 { Combinational ICs Three-state driver (bu er) s0 Module M0 a0 s1 Module a 1 M1 s2 Module a 2 M2 s3 Module a 3 M3 (c) 24 bus s0=s2=s3=0 s1=1 y Figure 3.16: c) Example of use of three-state drivers Introduction to Digital Systems 3 { Combinational ICs (enable) e x symbol 25 y y= { x if e=1 Z if e=0 function (a) V DD e x g pS e x g h pS nS open open y Z Z 0 1 y h nS 0 0 1 0 open 0 1 1 0 open 1 0 1 1 open closed 1 1 0 0 closed open three-state circuit (b) three-state circuit operation Figure 3.16: a) Three-state gate: symbol and function. b) Circuit and operation. Introduction to Digital Systems 3 { Combinational ICs Table 3.2: Characteristics of a family of cmos gates Gate type and and and or or or 26 Size equiv. gates] 2 2 3 2 2 3 1 1 2 2 4 5 6 1 2 4 4 5 6 3 6 3 6 2 2 Fanin 2 3 4 2 3 4 1 2 3 4 5 6 8 2 3 4 5 6 8 2* 3* 2* 3* 4 4 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Propagation delays t pLH ns] t pHL Load factor standard loads] 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.1 2.0 1.1 2.4 2.1 1.1 2.0 1.1 2.3 1.3 1.0 1.0 ns] not nand nand nand nand nand nand nor nor nor nor nor nor xor xor xnor xnor Introduction to Digital Systems 2-or/nand2 2-and/nor2 0 15 + 0 037 0 20 + 0 038 0 28 + 0 039 0 12 + 0 037 0 12 + 0 038 0 13 + 0 038 0 02 + 0 038 0 05 + 0 038 0 07 + 0 038 0 10 + 0 037 0 21 + 0 038 0 24 + 0 037 0 24 + 0 038 0 06 + 0 075 0 16 + 0 111 0 23 + 0 149 0 38 + 0 038 0 46 + 0 037 0 54 + 0 038 0 30 + 0 036 0 16 + 0 036 0 50 + 0 038 0 28 + 0 039 0 19 + 0 036 0 30 + 0 036 0 16 + 0 036 0 50 + 0 038 0 28 + 0 039 0 19 + 0 036 0 17 + 0 075 0 17 + 0 075 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L 0 16 + 0 017 0 18 + 0 018 0 21 + 0 019 0 20 + 0 019 0 34 + 0 022 0 45 + 0 025 0 05 + 0 017 0 08 + 0 027 0 09 + 0 039 0 12 + 0 051 0 34 + 0 019 0 36 + 0 019 0 42 + 0 019 0 07 + 0 016 0 08 + 0 017 0 08 + 0 017 0 23 + 0 018 0 24 + 0 018 0 23 + 0 018 0 30 + 0 021 0 15 + 0 020 0 49 + 0 027 0 27 + 0 027 0 17 + 0 025 0 30 + 0 021 0 15 + 0 020 0 49 + 0 027 0 27 + 0 027 0 17 + 0 025 0 10 + 0 028 0 10 + 0 028 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L 3 { Combinational ICs Levels of integration 27 Level of Technology Number of Integration transistors ssi bipolar 10 msi mos, bipolar 10-100 lsi mos, bipolar 100-10,000 vlsi mos, bipolar > 10,000 Typical functions Individual gates, ip- ops Adders, counters, registers ROMs, PLAs, small memories large memories, microprocessors, complex systems Introduction to Digital Systems 3 { Combinational ICs VLSI circuit-level design styles 28 Full-custom Semi-custom (standard cells) Gate-array (y = abd + a'c + c'd) y a' abd a b b' c c' c'd a'c d Vertical routing channel Horizontal routing channel z (z = a + b) Figure 3.17: Example of gate array. Introduction to Digital Systems 3 { Combinational ICs Packaging level: chips, boards, and cabinets Silicon wafer chip 29 pin Enclosed chip (IC package) chip-to-pin wire Figure 3.18: Silicon wafer, chip and integrated circuit package Introduction to Digital Systems 3 { Combinational ICs ICs PC boards IC IC 30 Printed circuit board (PCB) Connector Rack Backplane with connectors and wiring PC boards Cooling fans racks Power supply Cabinet with racks, PC boards and auxiliary equipment Figure 3.19: Packaging levels Introduction to Digital Systems 3 { Combinational ICs Packaging levels: Example 31 IBM 3081 central processing unit: Level of Packaging Module PC Board Subsystem (processor) System (CPU) Number of Size Components mm mm] 100{133 chips 90 90 6 { 9 modules 600 700 3 boards 2 subsystems Introduction to Digital Systems 3 { Combinational ICs ...
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This note was uploaded on 04/14/2008 for the course CS M51A taught by Professor Ercegovac during the Fall '07 term at UCLA.

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