# ch4 - DESCRIPTION AND ANALYSIS OF GATE NETWORKS 1 Gate...

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Unformatted text preview: DESCRIPTION AND ANALYSIS OF GATE NETWORKS 1 Gate networks Sets of gates: (AND OR NOT), NAND NOR XOR Analysis and description of gate networks Introduction to Digital Systems 4 { Gate Networks: Description and Analysis 2 Combinational system Combinational module Combinational module Figure 4.1: Hierarchical implementation of a module Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Gate networks 3 x3 x2 x1 x0 Figure 4.2: A gate network z1 z0 gates external inputs and outputs connections Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Gate networks (cont.) G0 G1 G2 (a) F =10 L =1 4 G1 G2 L =1 G3 illegal L =1 (b) G8 G1 G2 G1 G2 G3 (c) G3 (d) Figure 4.3: a) Illegal network connection. b) Acceptable output load. c) Loop-free network. d) Loop network Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Description of gate networks 5 logic diagram (graphical representation) net list (tabular representation) HDL description (program) x3 x2 x1 x0 1 2 1 2 3 A B 3 1 2 C 3 z 4 Figure 4.4: a) Graphical representation (logic diagram) Introduction to Digital Systems 4 { Gate Networks: Description and Analysis 6 Gate Type Inputs Output A and ; 2 A1 A3 From To A2 B and ; 3 B1 B2 B3 C or ; 2 C1 C2 Gates B4 C3 (b) x3 x2 x2 x1 x0 A3 B4 C3 A1 A2 B1 B2 B3 C1 C2 z Connections A_3 B_4 C_3 z <= <= <= <= x3 and x2 x2 and x1 and x0 A_3 or B_4 C_3 (c) Figure 4.4: Network representation: a) graphical b) tabular c) hdl-based. Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Characterization of a gate network 7 functional speci cation input load factors of the network inputs fan-out factor of the network outputs (only for some technologies) and propagation delays through the network. Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Universal sets of gates Set fAND,OR,NOTg 8 z = (((x0 x1)x2) x2x3 x4) 0 0 x0 x1 x2 x3 x4 Figure 4.5: Correspondence among switching expression and AND-OR-NOT network z Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Universal sets of gates (cont.) Sets fAND,NOTg and fOR,NOTg 9 x n; 1 x n; 2 : : : x : : : x0 = (x 1x 2 : : : x : : : x0) 0 0 0 0 0 i n; n; i x n-1 x n-2 z x1 x0 Figure 4.6: AND-NOT implementation of an OR gate Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Universal sets of gates (cont.) Sets fNANDg and fNORg 10 x = (xx) 0 0 NOT (x) = NAND(x x) x1x0 = ((x1x0) ) = ((x1x0) (x1x0) ) 0 0 0 0 0 AND(x1 x0) = NAND(NAND(x1 x0) NAND(x1 x0)) Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Universal sets of gates (cont.) 11 x x x' x (a) x1 x0 x1 x0 (b) Figure 4.7: Implementations with NAND gates: a) NOT b) AND x' 1 x' x1x0 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Mixed-logic notation 12 x n-1 x0 x n-1 x0 z z (a) z = (x n- 1 ... x1 x0) ' z = x' n-1 + ... + x'+ x' 1 0 x n-1 x0 x n-1 x0 z z (b) z= ( x n- 1 + ... + x 1 + x0 ) ' z = x' n-1 ... x' x' 1 0 Figure 4.8: Mixed-logic notation: a) NAND gate b) NOR gate Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Complex gate structures 13 x1 x0 XOR x1 x0 XNOR (a) z x3 x2 x1 x0 AND-NOR (b) z x3 x2 x1 x0 OR-NAND z z Figure 4.9: Additional gates in CMOS a) XOR and XNOR, b) Complex gate structures: AND-OR and OR-AND Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Analysis of gate networks 14 Functional analysis: 1. Obtain I/O switching expressions 2. Obtain a tabular representation of the (binary) function (if few variables) 3. De ne high-level input and output variables use codes to relate these variables with the bit-vectors 4. Obtain a high-level speci cation of the system Network characteristics: input load factors, fan-out factors, and delays Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Obtain switching expressions 15 i) Assign names to each connection in the network ii) Write switching expressions for each gate output iii) Substitute all internal names to obtain external outputs in terms of external inputs. Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Example x'0 x0 x'2 T1 T4 x1 x3 T5 Figure 4.10: Gate network for analysis 16 x'1 T2 x2 T3 T6 z1 z0 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Example (cont.) 17 Output expressions: z0 = T2 T3 = x0x1x2 x0T1 = x0x1x2 x0(x2 x3) = x0x1x2 x0x2 x0x3 0 0 0 0 0 0 0 0 z1 = T5 T6 = x1x2x3 = x1x2x3 = x1x2x3 = x1x2x3 Reduced expressions 0 0 0 T4 (T1x0x1) T1 x0 x1 x2x3 x0 x1 0 0 0 0 0 0 0 z0 = x0x1x2 x0x2 x0x3 (no reduction possible) z1 = x0 x1 x2 0 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Hierarchical approach 18 decompose the network into subnetworks (modules) analyze each subnetwork separately use substitution to obtain the network function Introduction to Digital Systems 4 { Gate Networks: Description and Analysis 19 y2 O1 M1 t N1 A1 A2 A3 A4 A5 A6 w2 y1 w1 y0 w0 x2 x1 x0 M2 O2 v2 N2 O3 v1 N3 O4 v0 N4 A7 A8 A9 A10 A11 M3 O5 O6 z2 z1 z0 Figure 4.11: Network for hierarchical analysis Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Example cont. Verify that the network satis es speci cation: Inputs: x y w 2 f0 1 : : : 7g Output: z 2 f0 1 : : : 7g Function: z = (y + 1) mod 8 (w + 1) mod 8 8 > < > : 20 if if x 6= 0 x=0 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Subnetworks M1 : 21 t = x2 x1 x0 8 > 1 if x 6= 0 < t= > : M2 : 0 otherwise 0 M3: v = y t 8 w t (i = 0 1 2) > y if t = 1 < v = > w if t = 0 : 8 > y if t = 1 < v = > w if t = 0 : i i i z2 = v2v1v0 v2v1 v2v0 z1 = v1v0 v1v0 z0 = v0 0 0 0 0 0 0 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Example (cont.) High-level speci cation: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 22 v2 v1 v0 z2 z1 z0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 ! v z 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 From table, we get Second level of analysis: 8 > < > : z = (v + 1) mod 8 if if (y + 1) mod 8 z = (w + 1) mod 8 x 6= 0 x=0 4 { Gate Networks: Description and Analysis Introduction to Digital Systems Analysis of networks with NOT, NAND and NOR x5 x'4 x3 x2 x1 x'0 4 3 2 3 1 23 z (a) x5 x'4 x3 x2 x1 x'0 4 3 2 3 1 z (b) x'5 x4 x'3 x'2 x1 x'0 4 3 2 3 1 z (c) Figure 4.12: a) NAND network b) Network redrawn in mixed-logic notation Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Analysis (cont.) 24 Use mixed-logic transformations z = x5 (x4 x3)(x2 x1x0) = x5 x4x2 x3x2 x4x1x0 x3x1x0 0 0 0 0 0 0 0 0 0 0 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis 25 x2 x'1 x'2 x1 x0 x'1 x'2 2 4 4 3 2 1 z x0 (a) x2 x'1 x'2 x1 x0 x'1 x'2 2 4 4 3 2 1 z x0 (b) x2 x'1 x'2 x1 x0 x'1 x'2 2 4 4 3 2 1 z x0 (c) Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Analysis (cont.) 26 z = ((x2 x1)(x2 x1) x0)(x2 x1 x0) = (x2 x1 x0)(x2 x1 x0)(x2 x1 x0) = (x2x1 x2x1 x0)(x2 x1 x0) = x2x1 x0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Analysis of Characteristics Load factor of a network input Fan-out factor of a network output Size of the network Network (propagation) delay Number of levels of a network Dynamic characteristics 27 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis 28 Table 4.3: Characteristics of a family of cmos gates Gate Fantype in AND 2 AND 3 AND 4 OR 2 OR 3 OR 4 NOT 1 NAND 2 NAND 3 NAND 4 NAND 5 NAND 6 NAND 8 NOR 2 NOR 3 NOR 4 NOR 5 NOR 6 NOR 8 XOR 2* : : : : : : : : : : : : : : : : : : : : : Propagation delays t pLH ns] t pHL Load factor Size standard equiv. loads] gates] 1.0 2 1.0 2 1.0 3 1.0 2 1.0 2 1.0 3 1.0 1 1.0 1 1.0 2 1.0 2 1.0 4 1.0 5 1.0 6 1.0 1 1.0 2 1.0 4 1.0 4 1.0 5 1.0 6 1.1 3 2.0 4 { Gate Networks: Description and Analysis ns] 0 15 + 0 037 0 20 + 0 038 0 28 + 0 039 0 12 + 0 037 0 12 + 0 038 0 13 + 0 038 0 02 + 0 038 0 05 + 0 038 0 07 + 0 038 0 10 + 0 037 0 21 + 0 038 0 24 + 0 037 0 24 + 0 038 0 06 + 0 075 0 16 + 0 111 0 23 + 0 149 0 38 + 0 038 0 46 + 0 037 0 54 + 0 038 0 30 + 0 036 0 16 + 0 036 : : : : : : : : : : : : : : : : : : : : : L L L L L L L L L L L L L L L L L L L L L 0 16 + 0 017 0 18 + 0 018 0 21 + 0 019 0 20 + 0 019 0 34 + 0 022 0 45 + 0 025 0 05 + 0 017 0 08 + 0 027 0 09 + 0 039 0 12 + 0 051 0 34 + 0 019 0 36 + 0 019 0 42 + 0 019 0 07 + 0 016 0 08 + 0 017 0 08 + 0 017 0 23 + 0 018 0 24 + 0 018 0 23 + 0 018 0 30 + 0 021 0 15 + 0 020 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : L L L L L L L L L L L L L L L L L L L L L Introduction to Digital Systems 29 y2 O1 M1 t N1 A1 A2 A3 A4 A5 A6 w2 y1 w1 y0 w0 x2 x1 x0 M2 O2 v2 N2 O3 v1 N3 O4 v0 N4 A7 A8 A9 A10 A11 M3 O5 O6 z2 z1 z0 Figure 4.14: Network for hierarchical analysis Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Example (cont.) Types of gates used: 2-input AND, 3-input AND, etc. Load factors. network inputs: 1 gate inputs: 1 30 Fanout factors. F = 12 (assumed) F (z2) = F (z1) = 12 F (z0) = 12 ; 2 = 10 Network size : 38 equiv. gates] 21 actual] Number of levels: 7 Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Network delay The longest path: 31 O1 ! N1 ! A2 ! O2 ! N2 ! A9 ! O5 TpLH (x1 z2) = tpLH (O1) + tpHL(N1) + tpHL(A2) + tpHL(O2) +tpLH (N2) + tpLH (A9 ) + tpLH (O5 ) TpHL(x1 z2) = tpHL(O1) + tpLH (N1) + tpLH (A2) + tpLH (O2) +tpHL(N2) + tpHL (A9 ) + tpHL(O5 ) Gate Identi er Output load tpLH tpHL OR3 NOT AND2 OR2 NOT AND3 OR3 O1 N1 A2 O2 N2 A9 O5 L 4 3 1 3 1 1 ns] ns] 0.27 0.43 0.13 0.10 0.19 0.18 0.23 0.26 0.06 0.07 0.24 0.20 0:12 + 0:038L 0:34 + 0:022L TpLH (x1 z2) = 0:27 + 0:10 + 0:18 + 0:26 + 0:06 +0:24 + 0:12 + 0:038L = 1:23 + 0:038L ns] TpHL(x1 z2) = 0:43 + 0:13 + 0:19 + 0:23 + 0:07 +0:20 + 0:34 + 0:022L = 1:59 + 0:022L ns] Introduction to Digital Systems 4 { Gate Networks: Description and Analysis Timing diagram 32 x1 x0 x1 x2 S z0 z1 z2 T z2 pLH T pHL Figure 4.15: Timing diagram from network analysis Introduction to Digital Systems 4 { Gate Networks: Description and Analysis ...
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## This note was uploaded on 04/14/2008 for the course CS M51A taught by Professor Ercegovac during the Fall '07 term at UCLA.

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