Ch5-1 - EE 306 Introduction to Computing Chapter 5: The...

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1 Ramesh Yerraballi 5-1 EE 306 Introduction to Computing Chapter 5: The LC-3 Instruction Set Architecture (Part 1 of 2)
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2 Ramesh Yerraballi 5-2 ISA Overview Memory Address space Addressability: Word or Byte Registers Number Type Instructions Operations Data Types Addressing Modes
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3 Ramesh Yerraballi 5-3 LC-3 Memory Organization addressability word (16 bits/location) address space 2 16 locations = 64k 2 9 words/page = 512 2 7 pages =128 page location in page [8:0] [15:9] Address [16:0]
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4 Ramesh Yerraballi 5-4 General Purpose Registers (GPRs) Registers Special “memory” that is “inside” the CPU Very fast access: 1 clock cycle. General Purpose Registers: addressable by an instruction (visible to the user). Other registers may not be accessible (not architectured) LC-3 8 general purpose registers: R0,R1,. ..,R7 •a register can hold any 16 bit pattern - i.e. data or addresses 1111 1111 1111 1000 Register 7 (R7) 1111 1111 1111 1010 Register 6 (R6) 1111 1111 1111 1100 Register 5 (R5) 1111 1111 1111 1110 Register 4 (R4) 0000 0000 0000 0111 Register 3 (R3) 0000 0000 0000 0101 Register 2 (R2) 0000 0000 0000 0011 Register 1 (R1) 0000 0000 0000 0001 Register 0 (R0) 1111 1111 1111 1000 Register 7 (R7) 1111 1111 1111 1010 Register 6 (R6) 1111 1111 1111 1100 Register 5 (R5) 1111 1111 1111 1110 Register 4 (R4) 0000 0000 0000 0111 Register 3 (R3) 0000 0000 0000 0100 Register 2 (R2) 0000 0000 0000 0011 Register 1 (R1) 0000 0000 0000 0001 Register 0 (R0) 1 0 0 1 R1 0 2 0 3 0 4 0 5 0 6 0 7 R0 0 8 0 9 1 1 0 R2 0 1 1 1 1 2 0 1 3 0 1 4 ADD 0 1 5
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5 Ramesh Yerraballi 5-5 Instructions Two main parts Opcode: specifies what the instruction does. Operand(s): what the instruction acts on
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This note was uploaded on 04/17/2008 for the course EE 306 taught by Professor Ambler during the Spring '07 term at University of Texas at Austin.

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Ch5-1 - EE 306 Introduction to Computing Chapter 5: The...

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