ece prelab3 - 1 2 SW1 1 3 OUT1 1 3 OUT1 1 7 GND 1 7 GND 1...

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Lab #3; THE UNIVERSAL LOGIC GATE 9-27-07 Name: Jeff Rose Objective: The objective of this experiment is to become familiar with the logic gates which are available to the digital designer. Performing this laboratory exercise will help the student become aware of the multiple uses of the NAND gate, acquaint the student with a method of implementing the six basic logic functions out of this universal gate, and provide the student an opportunity to write another clear and concise report which includes a procedure, preliminary and actual data, and conclusions. Equipment Needed: IDL-800 Digital Lab Wire Leads 1 7400 TTL Integrated Circuit 1 Logic Probe Gates Symbols: 1. 2. 3.
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4. 5. 6. Wiring Diagram: Wiring Table: 1. 2. From To From To Chip Pin Chip Pin Chip Pin Chip Pin 1 1 SW1 1 1 SW1 1 2 SW0
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Unformatted text preview: 1 2 SW1 1 3 OUT1 1 3 OUT1 1 7 GND 1 7 GND 1 14 +5 V 1 14 +5 V 3. 4. From To From To Chip Pin Chip Pin Chip Pin Chip Pin 1 1 SW1 1 1 SW1 1 2 SW0 1 2 SW1 1 3 1 4 1 3 1 10 1 3 1 5 1 4 SW0 1 6 OUT1 1 5 SW0 1 7 GND 1 6 1 9 1 14 +5 V 1 8 OUT1 1 14 +5 V 5. 6. From To From To Chip Pin Chip Pin Chip Pin Chip Pin 1 1 SW1 1 1 SW1 1 2 SW0 1 2 SW1 1 3 1 5 1 3 1 10 1 3 1 9 1 4 SW0 1 4 SW1 1 5 SW0 1 6 1 12 1 6 1 9 1 7 GND 1 7 GND 1 8 1 13 1 8 1 12 1 10 SW0 1 8 1 13 1 11 OUT1 1 11 OUT1 1 14 +5 V 1 14 +5 V Calculations: 1. 2. 3. 4. 5. 6. SW1 SW0 F SW1 F SW1 SW0 F SW1 SW0 F SW1 SW0 F SW1 SW0 F 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...
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This note was uploaded on 04/18/2008 for the course ECE 543 taught by Professor Rucinska during the Spring '07 term at New Hampshire.

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ece prelab3 - 1 2 SW1 1 3 OUT1 1 3 OUT1 1 7 GND 1 7 GND 1...

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