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**Unformatted text preview: **STUDENT NAME: lllllllllllIlllllllllllllﬂlllllllllIII|I|l NS
Brigham Young University Department of Electrical and Computer Engineering ECEn 220 — Sections 001 and 002
Exam #2
March 2 ~ March 4, 2016 Instructor: David Penry K5”
4/1 Please read the following instructions: 1. ECEn 220 — Exam # 2 This is a CLOSED BOOK exam. No books, notes or other information of any kind are allowed.
You may NOT use a calculator, cell phone or any other electronic device during this exam. It takes approximately 2 hours to complete this exam. YOU MUST write on this examination paper, showing your work to receive partial credit. Credit will not be earned for things I cannot read. If you need more paper, you may bring up to 15 sheets of blank scratch paper or a blank
Examination Blue Book into the examination area for working problems, but must transfer your
work to this exam paper. Any Blue Book you use must be discarded at the end of the exam. I will
not look at blue books or scratch paper. . There are 10 pages to this exam. Make sure you have all pages before beginning. Laws and theorems of Boolean algebra and Verilog operators are listed on the last two pages of
the exam. There are a total of 20 problems on this exam. Each problem is worth 4 points; partial credit of 1
point will be given for an incorrect answer that demonstrates some understanding of the problem. Do not get hung up and spend excessive time on any one problem at the expense of the others. If
you are having trouble solving one problem, move on and return to it later. Observe the University Honor Code. All work on this exam must be your own. Winter 2016 Page 1 of 10 1. Convert 37.62510 to binary. z
113/“ xeiéag [OUlO‘o‘Ol2
L /
2 (<0 LZs’o
{/71 K1 5
1L. gaff
ZLé KO 0,50
3U [80 7\ Z"
0 RI 2. Convert 11000112 to base 10. ¢ -3
ZBVZZ+ZZVZ : j1_37§'° 3. What decimal values does this BCD code 0101 0111 lOOOBCD represent ? g 7 9 l o
4. Show the expression connected to input I0 when you realize the following function using a 4:1
multiplexer with control inputs of A and B in that order (A is the
most signiﬁcant select bit). D
F=A’B+AC+BD+A’D z
A : O
6 :0 C F: j«o+ O-C'fD‘D-fj-93D ECEn 220 — Exam # 2 Winter 2016 Page 2 of 10 5. Show the implementation of the function F = (A’+C’)B using a 3:8 decoder plus one additional
gate. 6. Show the contents of address 1310 when you realize the following functions using a 16 x 2 ROM. Assume that A is the most signiﬁcant bit of the address and that D is the least signiﬁcant bit of
the address. F1=A’B+BD’+A’BC+ABC’ 13w: “0'2
F0=AB+AC+A’D’ Ff'
ask 7. What is the delay of the critical path through this circuit? m AND2 3 ns
AND3 5ns
AND4 7ns NAND2 2 ns
NAND3 4ns
NAND4 6ns
0R2 4ns
0R3 6ns
0R4 8ns
NOR2 3ns
NOR3 5ns
NOR4 6ns XORZ 5ns
XORB 7ns ECEn 220 — Exam # 2 Winter 2016 Page 3 of 10 l/Z/IS 8. Add the following 8-bit 2’s-complement binary numbers. What is the 2’s-complement sum? LlJl\
10010101
01111110 000:0“le ‘ A r k Joe} VL
car/‘7 M 6 52+ faﬂL 6°C we 3 gm
Mixed}: ave/Maw 51/ 9. The decimal value ofthe 2’s-c0mplement binary number 10011010 is: ,Z7zr ZHXZ3+Zij “’02”, 10. The 9-bit binary representation of the decimal value 137 (using 2’s—complement) is:
Z. {3 7 I o
aégkl (9 OOIOO/a/
a 133 m
Z &7 m
Z Li I"
a lﬂ “0
7. (f “w
[k D
2% A l
11. The 9-bit binary representation of the decimal value -226 (using 2’s-complement) is:
W “216 a —Zb’é +30 1L3};
1’ 7‘ l; R0
(92+? 2 in
5 L1 /< /
1L3 R l
2U R ’
o R \ [COOHHOZC ECEn 220 — Exam # 2 Winter 2016 Page 4 of 10 12. The logic circuit shown below has inputs A, B, and C shown by this timing diagram. Draw the timing
diagram for output Y. Each gate has a delay of 10 ns. Each increment on the timing chart is 10 ns. 13. Draw the schematic for a gated D latch. ECEn 220 — Exam # 2 Winter 2016 Page 5 of 10 14. Consider the Circuit below. Given the following gate delays, what is its Clock-to-Q delay? {Norzz Us
{An}: 8 115
{NOR : 5 HS eon 3 ins 4’ Zws +2“ + 5/,4'5 +5n5 rbn: ZL/ng 15. For the circuit in the problem above, what is its setup time?
A : étpu iii/51491 Z‘GMA ’- (2' gut-0U)
: Znat‘grxs fZ-Jrrxs " Z'ZMLS 2 lérxs but, 16. Consider the circuit from the previous problem. What is its hold time? ékle : Z'éimu: 4R3 17. The following module describes a Circuit. What is the value of q when a = 0111 and b = 0101? Show
your work. module problem(a, b, q);
input[3:0] a, b;
output[l:0] q; assign q[l] &({2{2'b10}}[~(aAb));
assign q[0] (b<(a>>l))?1'bO:1'bl; endmodule ELZL1L°(03?‘A¢:WA&> :1010
QL 3 = l ECEn 220 — Exam # 2 Winter 2016 Page 6 of 10 18. Draw the schematic of the circuit described by this Verilog module. module problem(q, a, b, c, d, e);
input[1:0] a;
input[15:0] b, c, d, e;
output[15:0] q; assign q = a[0] ? (a[l] ?C§>: c) : (a[1] ? b : d);
endmodule 6L ncjily’ Valid . git/7.4173
gK¢—C_ LgﬁJ%L§
c; N19» 0):”:4/ Mid"
G g l jk \Q é /4’0 0+ “9U accguoéﬂf "5
E / u
i\$’(09) 2
f g / Jr a ( wat$ o—K‘O c—fc curred»
I/‘(fé 6
aﬁ'iﬁb tc‘ vow-5 “J90 5484's 0A) ‘1/“43 M Lei/weak) wiregﬂtr
016°” “5 {M7 6'5 ECEn 220 — Exam # 2 Winter 2016 Page 7 of 10 20. Draw the schematic for a 3—bit ripple-carry adder built using full adders (you can use an appropriate symbol
for a full adder). Do not forget to clearly label inputs and outputs. ECEn 220 — Exam # 2 Winter 2016 Page 8 of 10 ...

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