midterm-2013_solution - ECE 553 Testing and Testable Design...

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ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2013-2014 Midterm Examination CLOSED BOOK Kewal K. Saluja Date: November 12, 2013 Place: Room 2535 Engineering Hall Time: 7:15 - 8:30 PM Duration: 75 minutes PROBLEM TOPIC POINTS SCORE 1 General Questions 10 2 Test Economics 16 3 Modeling 11 4 Fault Simulation 14 5 SCOAP Computation 10 6 Test Generation - Comb 14 7 Test Generation - Seq 10 8 Checking Sequence 15 TOTAL 100 Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): SOLUTION First Name: ID Number: 1 Fall 2013 (Lec: Saluja)
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ECE 553: Testing and Testable Design of Digital Systems 1. ( 10 points ) General Questions Answer the following in brief and to the point. You must not use more than two to three lines of explanation where an an explanation is needed. (a) ( 1 point ) Memory usage by a concurrent fault simulator is smaller than the memory usage by a deductive fault simulator. Answer False. (b) ( 1 point ) Memory usage by a serial fault simulator is smaller that the memory usage by a deductive fault simulator. Answer True (c) ( 2 point ) A gate level fanout-free realization of a circuit has 20 inputs and 2 outputs. What is the maximum number of tests we will need to test this circuit. Hint: think checkpoints. In a fanout free circuit there are no branches. Therefore only checkpoints in the circuit are primary inputs. Hence the total number of faults for which we need to find tests is 2x20 = 40. Thus the max number of tests is 40. (d) ( 2 points ) If a fault f 1 dominates fault f 2 , and the fault f 2 dominates a fault f 3 . which of these faults can be deleted to reduce the fault list for fault detection. Give reason. We delete the fault that dominates. Hence delete faults f 1 and f 2 . (e) ( 1 point ) Method of Boolean Difference can be used to determine if a fault in a combinational circuit is redundant. Answer True (f) ( 1 points ) Easy/Hard heuristic can only be used in PODEM during backtrace and it can not be used during D-drive. Answer False. (g) ( 1 points ) If SCOAP CC0 value of a line in a circuit is 25 then it means that this line can always be set to 0 by assigning appropriate values to the inputs to the circuit. Answer False. (h) ( 1 points ) If SCOAP CC1 value of a line in a circuit is inf then it means that this line can never be set to 1 no matter what values are assigned to the inputs to the circuit. Answer True 2 Fall 2013 (Lec: Saluja)
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ECE 553: Testing and Testable Design of Digital Systems 2. ( 16 points ) Test Economics A chip manufacturer is to produce ICs in a very large quantity and it has worked out its cost as follows: . Cost of design (amortized on each IC) = $ 5.00 . Production cost of each IC = $ 1.00 . Test cost for each IC = $ 2.00 Test as filter has the following properties based on the quality of test: . 95% of the truly good devices will pass the test.
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