midterm-2014_solution - ECE 553 Testing and Testable Design...

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ECE 553: Testing and Testable Design of Digital Systems Department of Electrical and Computer Engineering University of Wisconsin–Madison ECE 553 : Testing and Testable Design of Digital Systems Fall 2014-2015 Midterm Examination CLOSED BOOK Kewal K. Saluja Date: November 11, 2014 Place: Room 2535 Engineering Hall Time: 7:15 - 8:55 PM Duration: 100 minutes PROBLEM TOPIC POINTS SCORE 1 General Questions 10 2 Test Economics 15 3 Logic and Fault Modeling 16 4 Fault Simulation 10 5 SCOAP Computation 10 6 Test Generation - Comb. 16 7 Test Generation - Seq. 11 8 Checking Sequence 12 TOTAL 100 Show your work carefully for both full and partial credit. You will be given credit only for what appears on your exam. Last Name (Please print): SOLUTION First Name: ID Number: 1 Fall 2014 (Lec: Saluja)
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ECE 553: Testing and Testable Design of Digital Systems 1. ( 10 points ) General Questions Answer the following in brief and to the point. (a) ( 1 points ) Give one reason as to why a circuit that is tested good may fail when a customer uses it. Less than 100% fault coverage Presence of faults not modeled by the fault model Damage during shipping ... (b) ( 1 points ) Give one reason as to why a circuit that is functionally correct may fail during testing. Excessive power drawn during test may cause the device to damage or fail “Design of Test” hardware may be faulty ... (c) ( 1 points ) What defect model is used to derive the yield equation in the paper by William and Brown included in the reading material? Random defects (d) ( 1 points ) If a fault f 1 is equivalent to f 2 and the fault f 1 dominates a fault f 3 , then which of these fault or faults must be included in the reduced fault list for the purpose of fault detection. Keep the faults f 3 in the reduced fault list. Fault f 1 is equivalent to f 2 , therefor we can remove either one of them. In par- ticular we can delete f 2 . Next f 1 dominates f 3 , therefore we can delete f 1 . (e) ( 1 points ) A single output combinational circuit is simulated using 3-value logic with some inputs specified (0s and 1s) while other inputs not specified (Xs). The output of the circuit is found to be a constant (0 or 1). Prove by proper reasoning or by an example that for the same input values and in the presence of a stuck-at fault in the circuit the output can be X. Use only the space provided. A simple example will be to consider a NAND with two inputs A and B. For A =0 and B = X, the output will be 1. Now in the presence of a fault A s-at-1 the faulty gate will produce an output X. 2 Fall 2014 (Lec: Saluja)
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ECE 553: Testing and Testable Design of Digital Systems (f) ( 1 points ) A combinational circuit test algorithm which is complete can deter- mine if a given fault in the circuit is redundant. Answer True or False. It is TRUE (g) ( 1 points ) Circuits which have high fault coverage using Random Patterns are called Random Pattern ...... TESTABLE ................ Circuits.
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