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Unformatted text preview: ‘~— e — - 7 ~ 7 ever v » 7- v—— .- -n---D -—-wv-----v --—- - —- -; -A “uni-AAA-Au x nuu VA, uni»; ‘WCJ- U... FThls is the text version of the file httg:l/www—csetpcsd.edufclaseeg’fgiofitgeeZGOIE[15335. G o o g i e automatically generates text versions of documents as we crawl the web. TO link to Oi" bookmark page, USE the following Ul'i: http : //w=.-m.google. com/sea:ch?q=cache- 19'? 6* ZRZGXOJ:www- cse .ucsd. edu/classes/fao6/cse200/ln2 .ps+LECTURE+NCTES+ON+MM+MACEINES &hl=en&ct=clnkécd=l&gl=in Google is neither afiHiated with the authors oftht's page nor reqyomsx‘bt’efor its content. These search terms have been highlighted: lecture notes ram machines CSE zoo Lecture Notes Turing machine vs; RAM machine; VSt Citron Chris Calabro October 26, 2006 1 RAM model There are many possible, roughly equivalent RAM models. Below we wiii o‘eiins one in the fashion of a RJSC computer and than show how to efficiently simulate common additional features. A RAM machine is a tuple R : (k, 5) where LL \7 is the number ofvariablo registers, and 5 is a finite program. A program 6; is a- finite sequence of statements. A statement is one of -R i<—M[R j](load} v M[R Lie—R j (store) "R ; *--R i —R j (subtract) ' R i ‘— R i div 2 (shift right) a R . <— I (load constant 1) ° ifR ; Z 0, goto L (conditional jump) - accept ° reject where i i V“- TL"! and I. r: T13” {We r-nnlrl ‘Fnrmaii’ze A statement 2:: a ifinle http://72.14.235.104/soarch?q=cachezj976—ZR26X03:va—csencsdcdu/olasses/faOtS/cseZO... 2/28/2607" U LJLIULUAK/ lVULk/D L L11L115 lilab'llillb VD. LULJVL lilablllllb VD‘ bLLLLilLD p. 9 (TC ('1 |\ “me .,J _ w m... .. __ Us”. \ .. c Wm- Mum.“ a “swam” W a ...p.c containing an opcode and the indexes of the operand registers or immediate constants, but little would be gained.) With these operations it is easy to see that we can simulate in 0(1) time each of the following: load the constant 0; addition; unconditional jump; jump if equal, unequal, less than, greater than, 1 mod 2; shifi left. Since we are mostly concerned with the performance of a machine only up to a constant factor, we may assume that our machine has these capabilities when less than or equal; compute R we want to stress the power of the machine, but may assume it only has the original instruction set when we want to stress the limitations of the machine, e. g. if we are trying to simulate an arbih‘ary RA M machine. Lei The total state of the machine at any given time is the values in the regisw ters, the location of the program counter. and the values in the memory cells « formally a tuple (R 1, . . . , R k , c, M) where each R 1 i Z, c L [55th and M : I) —-+ Z where D E Z is finite, The initial state is (x, O, . . . , O, L Li) where X l: N is the input. Ifthe state ofthe machine at time t is (R 1 , . . . , R k , c, M), then either In cth statement in 5 is acceptor rej ect= in which case the machine halts, or the state of the machine at time t + 1 is the result of executing the cth statement of 5, which at this point the reader should be able to formalize. The language of R is the set of decodings of natural numbers that R accepts. A natural encoding scheme is to fix a (strictly) positive integer for each letter in the alphabet and represent a string by ’concatenating’ together the encodings of each individual letter. Formally, fix some map f : E a Z 31 and extend f a homomorphism f D 1 Z a He Z is by he} fl )= fix 02 "‘2 i=0 where tn = lg max 1.3; f(a) + l is the length of the binary encoding of a single letter. An alternative is to assume 2 : {0, 1} and just tack a leading 1 onto the http://72. 14.235 .104/search?q=cache:j976—ZR26on:WWW—cse.ucsd.edu/classes/faoolcseZO... 12/289,007 jUU LCCLUIB l\‘ 0138 1111‘ng macnme VS. ELAN! machine VS. CITCUITS rage 3;- OT f string to encode it. Choose your favorite scheme. Notice that multiplication is not in our instruction set. Nor is writing a register in a bit whose index is given by another register. In general, these operations cannot be simulated in a number of steps polynomial in the bit size of the input. 7 1.1 Simulation on a l—tape TM We claim that we can simulate t steps of Mir) on a l-tape TM T in time 0(t 3 {n + t) 2 ). To initialize T, we decode x (by padding the left with a 1 bit, or whatever scheme we chose above) followed by k # symbols. These will delimit our representations of the k registers and the memory cells. This takes 0(n) time. The finite program of R can obviously be encoded in the transition fimction of T, the details of which would be extremely tedious but not very enlightening. The (finitely many) memory cells of R that contain nonzero values will be represented en a sequence of pairs w an address, a comma. a value= and a # - following the last used to represent the registers. The method we employ to simulate 1 step of R will depend on the laind of step. To simulate a load, we compare the value in the source register with the addresses in the simulated memory cells. Suppose R contains 1 registers ant. nonzero memory cells, and the largest size of a value in a register or memory cell or nonzero memory cell address is m. To compare a register with the ith memory address takes time 0(lm 2 ), and so to find the COtTCCt memory cell takes time 00 3 m 2 ). To copy it to the destination register may require pushing the contents of the tape after the destination register to the right by as much as so n '2 that the data can fit in the register. This takes time O(lm ‘ T m“: 7. Ct} To simulate a store is similar. All of the other operations can be carried out at least as fast. The instruction set was chosen carefully so that at each time step, in, 1 can each increase by at most 1. (notice that multiplication would have allowed m http://72.14.235. 104/ search?q=cache: j 976-2106on :www~cse.ucsd.edu/ classes/fa06/ ese20... 2/28/2007 vs. RAN; maciune vs. UlrL'iiu's 4UU Lecture Notes luring macnme 11AM macnme vs. Circuits - rage a U). ,r to double in one step) So at each of the first t steps, m S O(n+t) and i S 0(t). So T can simulate t steps of R in time O(t 3 (n + t) 1.2 Simulation of a I—tape TM We can simulate 1; steps of a l-tape TM T on a RAM machine R in 00) time, and only using the registers - no extra memory cells are required. To do this, we represent the tape of_ T that is to the left of the tape head in R g of T that is at and to the right of the tape head in R 1 , but with the contents in and the i reverse order. (i.e. left most symbol in the least»significant bits) The reason for this is that R can access the low-order bits of a register in 0(1) time, but not the high-order bits, and we will need quick access to the bits near the simulated tape head. The state of T is represented by the program counter of R. initially the encoding of the input x will be in R 1 , and R 2 contains 0. simulate 1 step of T, we read the low 0(1) bits representing the first symbol in R 1 by using the bit shifting operations and simulate atransition by conditional jumps. We also write the symbol that '1' would write by using addition and then move the tape head left or right by using more bit shifting and addition. All this takes 0(1) time. To Simulatet such steps then takes 0(t) time. 2 Circuit model There are many circuit models, we wili describe one. A circuit C is a dag (directed, acyclic graph) with ordered children and with each non-minimal node v labeled with a gate (function) of arity equai to the indegree ofv and each minimal node labeled with an index (an integer representing the name of an input) and each maximai node labeled with an index (representing the of an output). A Boolean circuit allows oniy Booiean functions as gates. Not ail circuits are Boolean, eg. perceptrons, arithmetic circuits. The indegree of node is called its fanin. In this course, if it is not said otherwise, we wili use :circuit’ to mean Booiean circuit of maximum fanin 2 and with a single output node. We may occasionally restrict the gates as well, e. g. we may only aliow AND, OR, NOT. if we restrict ourselves to commutative gates, then we may ignore the ordering of the children of each node. We can represent circuits in other equivalent forms, such as by giving a tuple representation of the nodes and their children in some topological ordering. By assigning vaiues to the inputs, we can recursively assign values to each non—minimal node v, including the output, by evaluating the gate at v at the values of the children of v in the order prescribed by the graph. That this process WGZRZfionzwww-cse.ucsd.edu/classes/fa06/cse20_.. 2/28/2007 ., .UU Leoture motes t tiring Ill'ctUilluC vs. Mutt itinciiiiie vs. bliLLiJLb i (15“ H- U. , -—- Wvam-n WMle—rmv— sr—vr-Em-wrx'x'P-fiw WWW~,WWWW,WCHWAWB WWW. i mmmcwwww Page 4 does not depend on the topological ordering in which we choose to evaluate the nodes is the recursion theorem from mathematical logic. This induces a function from a number of bits equal to the number of input nodes to 1 bit, and so we have a model of computation. But each circuit has only a fixed number ofmputs and so only represents a finite function. We can get around this by talking about a circuit family C = (C .1 . C 1 i C ;. . . .') v each C n is a circuit on n inputs. Given an encoding function 1": 2 -—'~ {0. i} and lettingf G(x t ' ' ‘ X n )= f[x 1 ) r - r it): n )be its homomorphic extension to l. the language ofC is then L(C)={XE: :J lC tr am} if :[X})=1l- lt may be easier to simply assume that E : {0, l} and that f is the identity, so watcher: :IC .1 (X}:l}. But circuit families can compute things that Turing machines cannot. E .2. let L be. any language whatsoever. n be some reasonable encoding of integers into strings, and let C n output 1 ifn J L 0 else Each Such C n is just a single node outputting a constant. Then the family C : (C 0 , C 1 , C 2 , . . . ) is certainly not computable (neither the ith bit ofthe description of the circuit family given nor the value C n wouid output given 3 input of size n) ifL is not. Such a model of computation is called nonuniform, which is meant to suggest that there may not be a single finite object that describes the whole family of circuits. (the circuits in the family cannot be generated in a uniform manner) A common way to limit the power of circuits is to enforce a uniformity condition: say a circuit family C = (C o, C 1 , C 2 , . . . ) is pwuniform iffthere is a polynomial—time TM T that outputs C n on input 1 " . We claim that the languages decided by p—uniform circuit families are exactly the languages decided by polynomial time 'l‘Ms. To see this, suppose L is decided by a p-uniforrn circuit family generated by the polynomial time TM T. Then we can combine T with an algorithm that evaluates the circuit to create a polynomial time TM for L. Going the other way, suppose L is decided by a polynomial time TM T. Then given an input 1 n , we can constructin polynomial time a circuit C n that computes as T does by using the Cook tableau construction (see pg 255 of Sipser). Details are left to the reader. It should be noted that restricting the fanin to 2 was not so special. p- uniform circuits with fanin of k 2 2 are polynomially equivalent to those with http://72.14.235.104/search?q=cache:j976-ZR26X03:www—cse.ucsd.edu/c1asses/fa06/cse20... 2/28f2007 LUU .LAJLHLL‘AR/ LVULMZ} L uAJLLE llLauiiulv VB. 1\..'_ LLYL rights/1.3111» v.3. uLL‘u—uLLg ,; ‘5v U U; I fanin 01‘2, since one can simply replace a k fanin gate with 0(1) fanin 2 gates. 3 Conclusion The languages that can be decided with only a polynomial amount of resources (time to decide, or time to generate a circuit that decides in our models) is a Page 5 very robust notion, being equivalent in many different models. If we let P those languages decided using a polynomial amount of resources model M, then our results so far are P RAM. = P l-Iape'l‘M . = P k-lapc TM : P p-uniform circuit, fanin 2 = P p-uniform circuit, fanin k = arcuit and'we simply write P for any of the first 5 quantities. http://72.14.235.104/search?q=cache:j976-ZR26x0J:www-cse.ucsdedu/classes/faO6/cse20... 2/28f2007 ...
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