ENGG1203_Tutorial_2_Q - ENGG 1203 Tutorial Sequential Logic...

Info icon This preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ENGG 1203 Tutorial Sequential Logic 19/26 Sept Learning Objectives Calculate timing in sequential circuits Design a finite state machine News Ack.: HKU ELEC1008, ISU CprE 281x, PSU CMPEN270, Wikipedia
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Q1 Design a synchronous, recycling MOD-8 binary down counter with D FFs. 2
Image of page 2
Q2 Draw the timing diagram of the following circuit 3
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Q3 Convert from state transition diagram to truth table From truth table to K-map From K-map to circuit 4
Image of page 4
Q4 Design a 2-bit counter with input x that can be A down counter when x = 0 (… 11 10 01 00 11 …) A Johnson counter when x = 1 (… 00 01 11 10 00 …) 5
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon