ENGG1203_Tutorial_2_Q - ENGG 1203 Tutorial Sequential Logic...

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1 ENGG 1203 Tutorial Sequential Logic 19/26 Sept Learning Objectives Calculate timing in sequential circuits Design a finite state machine News Ack.: HKU ELEC1008, ISU CprE 281x, PSU CMPEN270, Wikipedia
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Q1 Design a synchronous, recycling MOD-8 binary down counter with D FFs. 2
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Q2 Draw the timing diagram of the following circuit 3
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Q3 Convert from state transition diagram to truth table From truth table to K-map From K-map to circuit 4
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Q4 Design a 2-bit counter with input x that can be A down counter when x = 0 (… 11 10 01 00 11 …) A Johnson counter when x = 1 (… 00 01 11 10 00 …) 5
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