ENGG1203_Tutorial_2 - ENGG 1203 Tutorial Sequential Logic...

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1 ENGG 1203 Tutorial Sequential Logic 19/26 Sept Learning Objectives Design combinational circuits Calculate timing in sequential circuits Design a finite state machine News Ack.: HKU ELEC1008, ISU CprE 281x, PSU CMPEN270, Wikipedia
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Q1 You want to design a multiplier using combinational logic. The circuit is intended to calculate x.y = m, where x is represented by two bits as x 1 x 0 , y is represented by two bits as y 1 y 0 , and the product is m, also represented in binary in a similar way. Complete the following table to verify the function of a multiplier: In general, if x is p bits wide, and y is q bits wide, how many bits do we need to represent m? 2 1 3 3 3 3 9 11 1001 We need p + q bits.
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Remember that we can build a half adder using two-input combinational logic gates. Let the inputs be u and v, while the sum is s and the carry out is c. Complete the design of the half adder using only 2-input logic gates. 3
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