385 Sp16 Lecture 8 - ECE 385 Digital Systems Laboratory...

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ECE 385 Digital Systems Laboratory Lecture 8 Lab 5: Multiplier in SV Zuofu Cheng, Deming Chen Spring 2016 Link to Course Website
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Experiment 5: Goals Design a 2’s Complement 8 -bit Multiplier unit in SystemVerilog using logic operations. Do not use SystemVerilog Arithmetic Operations. i.e. Do not use A = A + B; or A = A B; This includes shift operations (should be created using logic not SV operators) Follow Experiment-5 description in Lab Notes Bring your code on a memory stick Bring a detailed block diagram of your design Components, ports and interconnections labeled A Note on Cooperation with others You are encouraged to cooperate with others in the class. However, each team must write its own SystemVerilog source and Lab Report. You are permitted to exchange ideas, algorithms, high level flow charts and so on BUT NO Entities, Components, Architectures, or Files of any kind.
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Quick Re- cap about Two’s Complement The one’s complement of a binary number is defined as the value obtained by inverting all the bits in the binary representation of the number. Two’s complement is equivalent to taking the one’s complement and then adding one The fundamental arithmetic operations are identical to those for unsigned binary numbers Zero has only a single representation
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8- bit 2’s Complement Multiplication 00000111 7 (multiplicand) x 1 1 000 1 0 1 x (-)59 (multiplier) 00000111 (-)413 + 00000000x + 00000111xx +00000000xxx +00000000xxxx +00000000xxxxx + 00000111xxxxxx - 00000111xxxxxxx Subtract 1111111001100011
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4-bit Multiplier: Block Diagram 4-BIT ADD_SUB Register S Switches Register A Register B X 5th bit Commands (push buttons) 1. ClearXA_loadB 2. RUN (Execute) 3. Reset Commands (control) 1. SHIFT XAB 2. ADD ( A+S XA) 3. SUB ( A S XA) Sign extension SHIFT , ADD and SUB are derived signals from State Controller. They last only one clock cycle
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Experiment 5: Requirements Recommendation: create the following modules and their Procedural and Continuous assignments 8-bit Registers A and B with parallel load and shift right capability ( can use one from Expt. 4 ) Extend bit X, a D-flip flop or 1-bit Register
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  • Fall '09
  • PATEL
  • Addition, Binary numeral system, Enumerated type, Arithmetic shift

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