385 Sp16 Lecture 5 - ECE 385 Digital Systems Laboratory...

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ECE 385 Digital Systems Laboratory Lecture 5 Introduction to SystemVerilog and Lab 4 Zuofu Cheng, Deming Chen Spring 2016 Link to Course Website
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Lab 4 Do Before Lab Session Install Quartus II on home computer or use EWS Windows machines (14.0 15.1 should be ok use Web Edition) Read Introduction to Quartus II (lab manual) Read Introduction to SystemVerilog (lab manual) Demo points (for next week’s lab session) 1 point do tutorial from Introduction to Quartus II and show testbench output 1 point design carry-ripple adder in SV and show analysis/waveform 1.5 point design carry-lookahead adder in SV and show analysis/waveform 1.5 point design carry-select adder in SV and show analysis/waveform
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FPGAs and SystemVerilog Done with TTL for the semester (after Lab 3) Will use SystemVerilog for the rest of the semester Understanding SV requires understanding underlying model of hardware This is analogous to learning to program in C in 120/220 Must understand principles of computers (bits/bytes, logical & arithmetic operations, instructions, memory) Can abstract away details of ISA (instructions, number of registers, memory architecture) SV is the same way, need to understand model & principles behind FPGAs, but do not need to be expert at FPGA architecture
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Programmable Logic Devices Evolved from PALs (Programmable Array Logic) and GALs (Generic Array Logic) and CPLD (Complex Programmable Logic Device) First generation devices (PALs) are one-time programmable ways to create combinational logical function Engineer writes logic expressions and defines I/Os on computer Software simplifies expression to SOP form and generates programming file Programming cable is used to set fuses / anti-fuses No memory / feedback elements limits applications Non-volatile (maintains design on power cycle)
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CPLD CPLDs (Complex Programmable Logic Devices) are one step more advanced than PAL/GAL. Integrates multiple levels of AND/OR logic with memory (flip flop) Typically used for simple designs with small number of logic elements with limited internal routing (feedback) Predictable delay due to limited routing options, low density by today standards Non-volatile (maintains design on power cycle)
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FPGA (Field Programmable Gate Array) We will be using FPGAs in this class (Cyclone IV) High density and designed for internal interconnects Fully programmable through bit-stream file Programmable Logic Programmable I/O Programmable Routing Programmable IO K LUT Inputs D FF Clock Out BLE # 1 BLE # N N Outputs I Inputs Clock I N Configurable Logic Block (CLB) Programmable Routing
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  • Fall '09
  • PATEL
  • Logic gate, Programmable logic device, Hardware description language, Field-programmable gate array, SystemVerilog

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