385 Sp16 Lecture 9 - ECE 385 Digital Systems Laboratory...

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ECE 385 Digital Systems Laboratory Lecture 9 Lab 6: SLC-3 Microprocessor Zuofu Cheng, Deming Chen Spring 2016 Link to Course Website
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Common SystemVerilog mistakes Treating SystemVerilog as standard programming language Languages like C and Java are designed for sequential computers HDLs like Verilog & SV describe digital hardware General hint, if you don’t know what hardware (MUX, FF, adder, decoder, etc …) code you are writing describes, you’re doing it wrong always comb begin if (a==b) begin reg_8 my_reg(.*); end else ... end ... end
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Common SystemVerilog mistakes What hardware is current_state describing? Is it consistent? If you have errors, always ask yourself what hardware you are trying to describe with each variable (is it a connection, a register, a latch…) If you don’t know how to write a description for given hardware building block, look at examples or ask enum logic [3:0] {A, B, C, D} current_state, next_state; always comb begin unique case (current_state) A: current_state = B; B: ... end endcase
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Lab 6: Goals (Week 1) Create SLC3 (Simplified LC3) microprocessor in SystemVerilog 16-Bit Data Path Memory-mapped I/O (only mapped peripheral is HEX displays using Mem2IO) Register File (8 registers with control) Other Registers PC, IR, MAR, MDR, nzp status register ALU and Memory Instructions Add, Sub, Logical Ops, Load, Store Control Flow instructions Branch and Jump Subroutine Week 1: Demo only FETCH operation Simulated and real memory May use SV arithmetic operators (e.g. a = a + 1;) Must pass timing and work at 50 MHz
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Week 1 Demo Simulation of PC loading into MAR and PC incrementing. (1 points) Use test_memory.sv Simulation of MDR loading into IR. (1 points) Use test_memory.sv Correct FETCH operation on the board, showing IR on the hex displays.
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