385 Sp16 Lecture 10 - ECE 385 Digital Systems Laboratory...

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ECE 385 Digital Systems Laboratory Lecture 10 SLC-3 Microprocessor cont. Zuofu Cheng, Deming Chen Spring 2016 Link to Course Website
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Lab 6: Goals (Week 1) Create SLC3 (Simplified LC3) microprocessor in SystemVerilog 16-Bit Data Path Memory-mapped I/O (only mapped peripheral is HEX displays using Mem2IO) Register File (8 registers with control) Other Registers PC, IR, MAR, MDR, nzp status register ALU and Memory Instructions Add, Sub, Logical Ops, Load, Store Control Flow instructions Branch and Jump Subroutine Week 1: Demo only FETCH operation Simulated and real memory May use SV arithmetic operators (e.g. a = a + 1;) Must pass timing and work at 50 MHz
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Week 1 Demo Simulation of PC loading into MAR and PC incrementing. (1 points) Use test_memory.sv Simulation of MDR loading into IR. (1 points) Use test_memory.sv Correct FETCH operation on the board, showing IR on the hex displays. Must use the physical memory (test_programs_image.ram) instead of the test memory (test_memory.sv). (3 point) Mem2IO block takes up 4 HEX displays as I/O peripheral, use other 4 for displaying IR Should halt after each FETCH so correct instruction can be seen on display Even though demo is simple, plan on finishing at least data-path this week, or week 2’s assignment will be impossible! Create all of the components in block diagram (register file, other registers, MUXes, ALU, branch logic, sign and zero extension blocks etc …) this week Dedicate next week to control unit state machine (IDSU) and debugging
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Available Documentation Lab 6 Materials in Lab Manual ISA breakdown (instruction coding for all 11 instructions) Execution summary (RTL description for FETCH, DECODE, EXEC) for each instruction Simplified block diagram Appendix C from P&P Detailed ISA description of LC3 Full block diagram (with MUXes & individual registers) Full state diagram Appendix A from P&P Detailed programming guide for LC3 Explains instruction encoding and has examples for each instruction
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Top Level Block Diagram Block diagram of FPGA top level CPU only has control (r/w), address, data I/O provided by Mem2IO block (memory controller & I/O mapper)
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