CPRE281_HW09_SOLUTION - Cpr E 281 HW09 SOLUTION ELECTRICAL...

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Cpr E 281 HW09 SOLUTION ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY Latches and Flip-flops Assigned Date: Eleventh Week Due Date: First class of 13th week 1 P1. (5 points) In the figure given below, a clock (CLK) and the input signal D are shown. Draw the resulting output signal Q for a positive edge triggered D flip-flop, negative edge triggered D flip-flop, and a D-Latch. Assume, Q = 0 initially. Sol: P2. (10 points) In class, we discussed that using a CLK input to the basic S-R latch serves as a “gate” which allows changes to latch state (Q output) only when CLK = 1 (latch is OPEN). This new circuit is a clocked SR latch (Lecture 23 Slides 6, 7, 8, and 9). The characteristic table of a clocked SR latch also has the undesirable inputs (R = 1, S = 1) which results in an oscillatory condition at Q output (slide 7). Draw the timing diagram for the clocked SR latch (refer to the circuit in slide 7) when the input is changed from R = 1, S = 1 to R = 0, S = 0 at the negative edge of the clock for each of the three cases below. The period of CLK is 2ns. a. Assume all gates have a delay of 1 ns. b. Assume AND gates have a delay of 1ns. The 𝑄 -NOR gate has a delay of 1 ns and the 𝑄 ̅ NOR gate has a delay of 2 ns.
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  • Fall '09
  • Flip-flops, Latch

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