CPRE281_HW10_SOLUTION

# CPRE281_HW10_SOLUTION - Cpr E 281 HW10 SOLUTION ELECTRICAL...

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Cpr E 281 HW10 SOLUTION ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY Registers and Counters Assigned Date: Thirteenth Week Due Date: April. 13, 2016 1 P1. (10 points) Consider a positive-edge triggered master-slave D flip-flop design, similar to the negative-edge triggered design in Fig. 9(a) but with the NOT gate in a different location. For the input Clock and D given below, draw a timing diagram of the positive- edge triggered flip-flop for Q m and Q s . Then briefly explain why this flip-flip design is positive-edge triggered. When the Clock is low, the master copies D to Q m and Q s is not changed. When the Clock is high, Q m is not changed and the slave copies Q m to Q s . Hence the only time that Q s (=Q) is changed is when the Clock is changing from low to high (i.e., positive clock edge). Then value stored in Q after the positive clock edge is the last value copied from D to Q m right before the Clock is switched to high.

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Cpr E 281 HW10 SOLUTION ELECTRICAL AND COMPUTER ENGINEERING IOWA STATE UNIVERSITY Registers and Counters Assigned Date: Thirteenth Week Due Date: April. 13, 2016 2 P2. (10 points) Draw the wave form of Q for a negative-edge triggered JK flip-flop given the following figure.
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