14_EEL4742-Notes#14 - Write cycle timing diagram is the...

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EEL4742 Notes # 14 ( 2 Lectures) Memory Types ROM- Read Only Memory A. Program once during the manufacturing, ROM B. Field Programmable once PROM C. Erasable by ultraviolet light EPROM D. Erasable by Electrical signal EEPROM or E2PROM E. Flash memory using a small capacitance to store a 1. ( can be written or erased many times) Random Access Memory RAM, loses information when power is removed. 1. Made from D-Flip Flops ( static RAM) 2. Made from a capacitor - Dynamic RAM. (needs to be refreshed periodically since the capacitor will slowly loose its charge, refreshing dynamic memory has resulted in different types of memory technology DRAM, DDR. For m=20, 2 20 = 1 Meg word, the decoder need 1 million lines instead of 1-D, memory is designed using 2 –D approach. General purpose processor timing diagram – to save Pin/s, the address lines and data (16 Bits) are time division multiplexed together. The data Bus is also bi-directional.
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Read cycle timing diagram
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Unformatted text preview: Write cycle timing diagram is the same except R/W = 0 __________________________________________________________________________________ __________________________________________________________________________________ Ex. Interface a 4K by 8-Bit memory to the processor. 2 m = 4K, m = 12 Memory function ce R/W data direction Function address direction 0 1 out of memory Read into memory into processor out of 74LS373 0 0 into memory Write into memory out of processor out of 74LS373 1 0 Tri-state Hold into memory out of 74LS373 1 1 Tri-state Hold into memory out of 74LS373 __________________________________________________________________________________ Typical memory timing diagram - 50 nsec part <<< Read >>> Data is valid 10 nsec after ce goes low, and is valid for 40 nsec. Data must be valid 50 nsec prior to ce OR R/W going back to 1 . Also the data must be valid no earlier than 10 nsec before ce OR R/W = 0....
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