lec04_-_sequential_logic (1) - Copy

lec04_-_sequential_logic (1) - Copy - Verilog for Digital...

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1 Verilog for Digital Design Chapter 3: Sequential Logic Design
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Review: Synthesis and HDLs
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Review: Structural Level Description
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Review: Continuous Assignment
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Review: Procedural Assignment with always
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Review: Mix-and-Match Assignments
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Review: case Statement
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Review: n -bit Signals
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Review: Incomplete Specification
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Review: Avoiding Incomplete Specification
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11 Sequential Logic Description using Hardware Description Languages Will consider description of three sequential components D Latch D Flip-Flop Registers Oscillators Controllers
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12 Latch and Flip-Flop
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Review: D Latch D Latch Symbol CLK D Q Q Two inputs: CLK , D CLK : controls when the output changes D (the data input): controls what the output changes to Function When CLK = 1, D passes through to Q (the latch is transparent ) When CLK = 0, Q holds its previous value (the latch is opaque ) Avoids invalid case when Q NOT Q Also called transparent latch or level-sensitive latch
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D Latch D Latch Symbol CLK D Q Q Verilog module D_latch(D, Clk, Q); input D, Clk; input Q; reg Q; always @(D or Clk) begin if (Clk) Q = D; endmodule The “if” construct When D or CLK change value: If CLK = 1, set Q = D Since there is no else, assignment occurs only when CLK = 1 Q follow D when CLK = 1 Q remain latched on CLK = 0 “always” construct triggered by chance in value of D or CLK Either change can cause the output to change The “always” construct Responds to changes in the signals on the sensitivity list: always @ ( D or Clk) Example is “level sensitive” When D or Clk changes value Make edge triggered by using Verilog keywords posedge and negedge i.e. always @ (posedge Clk)
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Review: D Flip-Flop Two inputs: CLK , D Function The flip-flop “samples” D on the rising edge of CLK When CLK rises from 0 to 1, D passes through to Q Otherwise, Q holds its previous value Q changes only on the rising edge of CLK A flip-flop is called an edge-triggered device because it is activated on the clock edge D Flip-Flop Symbols D Q Q
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D Flip-Flop Verilog module flipflop(D, Clock, Q); input D, Clock; input Q; reg Q; always @(posedge Clock) Q = D; // Q + = D, characteristic function endmodule D is not included on sensitivity list since it cannot cause output (Q) to change No transparent phase with edge triggered flip-flops: Characteristics function used in assignment statement Defining next state (Q + ) of the flip- flop D Flip-Flop Symbols D Q Q
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