Lab Report 3 - ECE-342 Lab 3: NMOS Characteristics...

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Unformatted text preview: ECE-342 Lab 3: NMOS Characteristics Stephanie Duy, Robert England Lab Group 4 October 29, 2007 Abstract This report describes the design and test of a voltage-controlled voltage amplifier. The amplifier uses an NMOS transistor in a CD4007 integrated circuit as a voltage-controlled resistance. The amplifier uses three LF351 op-amps, and requires ±12 V power supplies. The amplifier limits voltage inputs to above -200 mV to prevent device damage, and achieves a measured 19.5 dB gain with a 0 V input to the voltage controlling the CD4007's resistance, and 29.1 dB gain with a 1 V input to the control voltage. The amplifier has a corner frequency of 100 kHz at maximum gain. Component selection and test procedures are described. 1 Contents 1 Introduction 3 2 Circuit Design and Preliminary Analysis 4 2.1 Basic Amplifier Design 5 2.2 Control Input Scaler Design 7 2.3 Power Input Clamp Design 8 3 Simulated Performance 9 3.1 CD4007 Simulation 10 3.2 Amplifier Simulation 12 4 Experimental Implementation 15 4.1 MOSFET characteristics 15 4.2 Amplifier Analysis 20 4.2.1 Basic Amplifier Analysis 20 4.2.2 Control Input Scaler Analysis 21 4.2.3 Power Input Clamp Analysis 22 4.2.4 Complete Circuit Analysis 23 5 Discussion 28 6 Conclusion 29 A Design Calculations 30 A1 Control Input Scaler Design Calculations 30 A2 Power Input Clamp Design Calculations 32 A3 Control Input Scaler Experimental Calculations 34 B Calculating a Best-Fit Line______________________________36 2 1. Introduction This report describes the design and implementation of a voltage-controlled amplifier using the NMOS, or n-type MOSFET, of a CD4007 chip as a voltage- controlled resistance. The resistance characteristics of the MOSFET were tested by measuring the drain voltage and current of the device at specific gate voltages. These data points were then plotted, and the resistance obtained as the inverse of the slope of the linear (non-saturated) region of the plot. A non-inverting amplifier was then constructed to create a gain between 20 dB and 30 dB, controlled by a control voltage. In order to meet specifications, the amplifier included a clamp circuit to limit input signals to above -200 mV in order to prevent device damage, and a scaling circuit so that the control voltage produces a gain of 20 dB at 0 V, and 30 dB at 1 V. Section 2 details the process of designing the amplifier circuit, including the calculation of component values. Section 3 presents the results of a simulation of both a solitary transistor and the entire amplifier circuit. Section 4 presents experimental measurements taken on the amplifier circuit, and describes the process of finding a more accurate model for the NMOS. Section 5 summarizes the results of the amplifier. Appendix A contains the calculations for each section of the amplifier. Appendix B details the process of finding the best-fit linear approximation of a series of data points....
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This lab report was uploaded on 04/19/2008 for the course ECE 342 taught by Professor Hummels during the Fall '07 term at University of Maine Orono .

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Lab Report 3 - ECE-342 Lab 3: NMOS Characteristics...

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