VirtualMemory - Virtual Memory Prof Van Renesse Sirer...

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Virtual Memory Prof. Van Renesse & Sirer
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Segments Note: overloaded term… Chunks of virtual address space Access Protection User/Supervisor Read/Write/Execute Sharing Code, libraries Shared memory for IPC Virtualization Illusion of more memory than there really is Code Non-zero Init’d Data Zero Init’d Data + Heap Stack Code Non-zero Init’d Data Zero Init’d Data + Heap Stack Device Registers Kernel User Virtual Address Space 0
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Segment examples Code Execute-only, shared among all processes that execute the same code Private Data R/W, private to a single process Heap R/W, Explicit allocation, zero-initialized, private Stack R/W, Implicit allocation, zero-initialized, private Shared Memory explicit allocation, shared among processes, some read-only, others R/W
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MMU Translates virtual (or “logical”) addresses to physical addresses Enforces R/W/X protection Throws exceptions on illegal accesses Unit: “page” Typically 1, 2, 4, 8, or 16 Kbytes Often also tracks read and write accesses Physical page often called “page frame”
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Address Translation Scheme Address generated by CPU is divided into: Page number ( p ) – used as an index into a page table which contains base address of each page frame in physical memory Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit For given virtual address space 2 m and page size 2 n page number page offset p d m - n n
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Paging Hardware PTBR
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Implementation of Page Table Page table can be kept in main memory Page-table base register (PTBR) points to the page table Page-table length register (PRLR) indicates size of the page table In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction.
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Structure of the Page Table Hierarchical Paging Hashed Page Tables Inverted Page Tables Software vs. Hardware maintained… For portability, most kernels maintain their own page tables These have to be translated into MMU tables
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Hierarchical Page Tables Break up the logical address space into multiple page tables A simple technique is a two-level page table
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Two-Level Page-Table Scheme PTBR
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Two-Level Paging Example A logical address (on 32-bit machine with 1K page size) is divided into: a page offset of 10 bits (1024 = 2^10) a page number of 22 bits (32-10) Since the page table is paged, the page number is further divided into: a 12-bit page number a 10-bit page offset Thus, a logical address is as follows: page number page offset p i p 2 d 12 10 10
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Address-Translation Scheme PTBR
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Hashed Page Tables Common in address spaces > 32 bits The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location.
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