EE 3220 Test 1

# EE 3220 Test 1 - EE3220 Test 1 Name{5241 ft 1 Directions...

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Unformatted text preview: EE3220: Test 1 - 10/13/06 Name {5241/} ft! 1 Directions: This test contains 4 problems. You have 50 minutes to complete this test. Do not spend excessive time on any one problem. Partial credit will be given for partial knowledge. Provide answers in indicated spaces where applicable. Do not write in the table below. EE3220: Test 1 — 10/13/06 Name 2 1. For the following BJT inverter: (a) Create a complete small signal model. Do not neglect r0. (5 pts) (b) Derive the small signal gain from your model. (10 pts) (c) What is the small signal gain of an ideal voltage follower? How well does your answer match the ideal case? (5 pts) 10V s I? ,, I! Figure 1: BJ T Follower 5“ w 1} /7 eﬂ‘f I =- WWW //’ W 5 my man We» “’3' Y r "" A (if; I») :- 3/6 w‘ w J,» 7* 9%! [K V3491 r_ a 923 =- «yea?! ' m; a) 1»ng = +13», ﬂyflkﬂﬁ) =» ﬁx; Mm) "fag; .Zl‘ /}E + GM mat/M) rm! = a? 0km) m /’“ W *’ (ﬂw‘W'fa) Maﬁa?) 5 g i s: /ﬁ"m/n~ W,“ " :‘07' -. - I " :5 5"?) r7227m/ / , a? :3? 3 MW“ “W7 EE3220: Test 1 - 10/13/06 Name 3 2. For the CMOS inverter below: (a) Derive the small signal gain. Assume both devices operate in the constant current region. Do not neglect output impedances or the body effect. (15 pts) (b) Why is this circuit appropriate for digital systems? (5 pts) VDD C‘1 Vout Vin Figure 2: CMOS Inverter EE3220: Test 1 - 10/13/06 Name 4 3. Answer the questions below in order concerning the differential ampliﬁer pictured: (a) Choose RA such that Io is 5mA (5 pts) . (b) What are the resulting DC voltages at the collectors of the transistors? (5 pts) (c) What is the small signal diﬁ'erential gain to the collector of Q1 where vm = v1 -— v2? Neglect the output resistance. (5 pts) (d) What is the common mode gain to the collector of Q1? (5 pts) (e) Explain why the emitter node of Q1 and Q2 is eﬁectively a small signal ground for differential signals. (5 pts) (f) What is the best output conﬁguration to minimize common mode gain. Justify your response. (5 pts) 10V ‘p=1oo vA=2oo 6) 6?; if #53 are “3/ M Mg‘ mm”? {WI/71¢ ﬂ jgﬂ/ E ' 1.- ; « afar a y Mff’mrfe M? i=1” 51.: 1am?“ 11m ﬂrc/ a/fcrrﬂ—Jg ( ,9. , ,gl/é rmrrrw/ M?“ g. [’17 was f) 14+th « mfg a EE3220: Test 1 — 10/13/06 Extra Space Name EE3220: Test 1 - 10/13/06 Name 6 4. Create a 2-port small signal model for the ampliﬁer in ﬁgure 4 Where the input port is v1 — v2, and the output port is vow; referenced to ground. Ignore the body effect. Other reasonable approximations are acceptable. (30 pts) Figure 4: N MOS Differential Ampliﬁer EE3220: Test; 1 — 10/13/06 Extra Space Name ...
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## This test prep was uploaded on 04/20/2008 for the course EE 3220 taught by Professor Audiffred during the Fall '06 term at LSU.

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EE 3220 Test 1 - EE3220 Test 1 Name{5241 ft 1 Directions...

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