Homework 8 solutions

# Homework 8 solutions - Homework #8, due Tuesday 11/27/07 I....

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Homework #8, due Tuesday 11/27/07 I. (25%) An n + polysilicon-gate p-channel MOS transistor is made on an n-type Si Substrate with N d = 5 x 10 16 /cm 3 . The SiO 2 thickness is 10 nm in the gate region, and the effective interface charge is 2 x 10 11 /cm 2 . Sketch the C-V curve for this device showing the values of threshold and flatband voltages and the minimum and maximum capacitances. Fig. 6-17 may be helpful. V 293 . 0 cm / F 10 45 . 3 ) / Coulombs 10 602 . 1 )( cm / 10 2 ( V 2 . 0 2 7 19 2 11 = × × × = Φ = q C Q V i i ms FB V 402 . 1 cm / F 10 45 . 3 cm / Coulombs 10 144 . 1 V 788 . 0 2 2 7 2 7 = × × = + = FB i d ms T V C Q V φ 2 8 6 14 cm / F 10 30 . 7 cm 10 cm) / F 10 85 . 8 )( 8 . 11 ( × = × = = m d W C ε 2 8 2 8 2 7 2 8 2 7 cm / F 10 03 . 6 cm / F 10 30 . 7 cm / F 10 45 . 3 ) cm / F 10 30 . 7 )( cm / F 10 45 . 3 ( × = × + × × × = + = d i d i m C C C C C

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II. (25%) Problem 6.11 of text. Assume, specifically, that the B implant is right on the oxide/substrate interface.

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III. (25%) Problem 6.21 of the text.
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## This note was uploaded on 04/21/2008 for the course EE 339 taught by Professor Banjeree during the Spring '08 term at University of Texas.

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Homework 8 solutions - Homework #8, due Tuesday 11/27/07 I....

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