ELEC 4410 – lab6Dept. of ECE, HKUSTPage1of6ELEC 4410Lab 6: Post-Layout Simulation and Hierarchical LayoutVersion: Fall 2021Objective•In lab 5, you completed the inverter and nand2 layout designs, and they passed the DRC and LVSchecks. In this lab, you are going to perform the circuit simulation calledpost-layout simulationusing their extracted views (i.e. extracted netlists).•We developed the schematic view of the ring oscillator in lab 3 using the hierarchy designstructure, with theinvandnand2cells being the sub-modules of this design. The layout of thering oscillator will be built by use of the layouts ofinvandnand2cells.Post-layout simulationswill be carried out to see the difference in performance with different capacitive loads applied atthe output terminal.I. Standard-cells based designWe have developed some commonly used logic cells in our4410myLiblibrary.All cell layoutsshould be designed with afixed heightso that they can be abutted side by side to forms rows for sharinga common power and ground bus.Moreover, these fixed height cells can enable automated placementand routing of cells.Step 1.Ensure allthelayoutsofinvcell,nand2cell andbufcell having thesame height, if not, youshould correct them.•Re-run DRC and LVS checks if you make any changes on the layout views.II. The extracted view generation from the layoutCircuit extractionis performed after the layout design is completed.The circuit extractorgenerates an extracted view from a layout view.What is the use of the extracted view?The circuitextractor is able to estimate actual devices’ dimensions, interconnections and the parasitic componentspresent between layers from the layout view, this information is then stored in the extracted view.Thus,the resulting circuit simulation results obtained from its extracted view are a better estimation of thecircuit’s real performance.
