Quiz1F06 - EE319K Fall 2006 Quiz 1 Page 1 First Last This is a closed book exam You must put your answers on this piece of paper only You have 50

EE319K Fall 2006 Quiz 1 Page 1 Jonathan W. Valvano 01000001 September 29, 2006 10:00am-10:50am First:_________________ Last:_____________________ This is a closed book exam. You must put your answers on this piece of paper only. You have 50 minutes, so allocate your time accordingly. Please read the entire quiz before starting. (5) Question 1. Give the hex value….… (5) Question 2. Specify 0 or 1 ….….….…. (5) Question 3. Specify 0 or 1 ….….….…. (5) Question 4. Specify A-H ….……..…. (5) Question 5. Show the equation…. (5) Question 6. Show the machine code…. (5) Question 7. How many binary bits? ....... (5) Question 8. Specify values….……..…. RegA = RegX = (10) Question 9. Simplified memory cycles (you may or may not need all 5 entries) R/W Addr Data Changes to A,B,X,Y,S,PC,IR,EAR

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EE319K Fall 2006 Quiz 1 Page 2 Jonathan W. Valvano 01000001 September 29, 2006 10:00am-10:50am (25) Part 10a) Write the main program (figure shows the result after running your program) DDRM equ $0252 ; Port M Direction DDRT equ $0242 ; Port T Direction PTM equ $0250 ; Port M I/O Register PTT equ $0240 ; Port T I/O Register org $4000 main (25) Part 10b) Write the assembly language subroutine. ;*******Check*********** ; if PT6 is 1, then set PT5=1 ; if PT6 is 0, then return without modifying PT5 Check org $FFFE fdb main

EE319K Fall 2006 Quiz 1 Page 3 Jonathan W. Valvano 01000001 September 29, 2006 10:00am-10:50am aba 8-bit add RegA+RegB abx unsigned add RegX+RegB aby unsigned add RegY+RegB adca 8-bit add with carry to RegA adcb 8-bit add with carry to RegB adda 8-bit add to RegA addb 8-bit add to RegB addd 16-bit add to RegD anda 8-bit logical and to RegA andb 8-bit logical and to RegB andcc 8-bit logical and to RegCC asl/lsl 8-bit left shift Memory asla/lsla 8-bit left shift RegA aslb/lslb 8-bit arith left shift RegB asld/lsld 16-bit left shift RegD asr 8-bit arith right shift Memory asra 8-bit arith right shift asrb 8-bit arith right shift to RegB bcc branch if carry clear bclr clear bits in memory bcs branch if carry set beq branch if result is zero (Z=1) bge branch if signed ≥ bgnd enter background debug mode bgt branch if signed > bhi branch if unsigned > bhs branch if unsigned ≥ bita 8-bit and with RegA, sets CCR bitb 8-bit and with RegB, sets CCR ble branch if signed ≤ blo branch if unsigned < bls branch if unsigned ≤ blt branch if signed < bmi branch if result is negative (N=1) bne branch if result is nonzero (Z=0) bpl branch if result is positive (N=0) bra branch always brclr branch if bits are clear, brn branch never brset branch if bits are set bset set bits in memory bsr branch to subroutine bvc branch if overflow clear bvs branch if overflow set call subroutine in expanded memory cba 8-bit compare RegA with RegB clc clear carry bit, C=0 cli clear I=0, enable interrupts clr 8-bit Memory clear clra RegA clear clrb RegB clear clv clear overflow bit, V=0 cmpa 8-bit compare RegA with memory cmpb 8-bit compare RegB with memory com 8-bit logical complement to Memory