lect8 Finite State Machines

lect8 Finite State Machines - CSE140: Components and Design...

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1 1 Sources: TSR, Katz, Boriello & Vahid CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing 2 Sources: TSR, Katz, Boriello & Vahid Today HW#4 due now, HW#5 assigned Finish Latches/FFs Registers, counters Finite State Machines – Models for representing sequential circuits (Moore and Mealy) – Design procedure • state diagrams • state transition table • next state functions
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2 3 Sources: TSR, Katz, Boriello & Vahid DQ CLK positive edge-triggered flip-flop G CLK transparent (level-sensitive) latch D CLK Qedge Qlatch Comparison of latches and flip-flops 4 Sources: TSR, Katz, Boriello & Vahid Flip-Flop Types • SR flip-flop: like SR latch, but edge triggered • JK flip-flop: like SR (S Æ J, R Æ K) – But when JK=11, toggles –1 Æ 0, 0 Æ 1 • T flip-flop: JK with inputs tied together – Toggles on every rising clock edge • Previously utilized to minimize logic outside flip-flop – Today, minimizing logic to such extent is not as important – D flip-flops are thus by far the most common 3.5
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3 5 Sources: TSR, Katz, Boriello & Vahid Flip-Flop Set, Reset and Active Hi/Low Inputs DQ Q R Q’ AR D Q AS AR D Q cycle 1 cycle 2 cycle 3 cycle 4 clk D AR Q Q R 6 Sources: TSR, Katz, Boriello & Vahid Flip-flop features • Reset (set state to 0) – R – synchronous: – asynchronous: • Preset or set (set state to 1) – S (or sometimes P) – synchronous: – asynchronous: • Both reset and preset (set and reset dominant) –D n ew= n • Selective input capability (input enable or load) – LD or EN – multiplexor at input: – load may or may not override reset/set (usually R/S have priority) • Complementary outputs – Q and Q'
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4 7 Sources: TSR, Katz, Boriello & Vahid Q D Clk=1 R S 0 D’ 0 D’ D Q’ holds D’ when clock goes low holds D when clock goes low Negative edge-triggered flip-flop • Efficient solution: only 6 gates – sensitive to inputs only near edge of clock signal (not while high) 8 Sources: TSR, Katz, Boriello & Vahid clock data DQ Timing: Definitions D Clk Q T su 1.8 ns T h 0.5 ns T w 3.3 ns T pd 3.6 ns 1.1 ns T su 1.8 ns T h 0.5 ns T pd 3.6 ns 1.1 ns T w 3.3 ns
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5 9 Sources: TSR, Katz, Boriello & Vahid CLK1 is a delayed version of CLK0 In Q0 Q1 CLK0 CLK1 100 Clock skew 10 Sources: TSR, Katz, Boriello & Vahid Metastability clk D Q setup time violation metastable state ai synchronizer a
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This note was uploaded on 02/14/2008 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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lect8 Finite State Machines - CSE140: Components and Design...

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