lect13 verilog and basics

# lect13 verilog and basics - CSE140: Components and Design...

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1 1 Sources: TSR, Katz, Boriello, Vahid, Perkowski CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing 2 Sources: TSR, Katz, Boriello, Vahid, Perkowski Announcements and Outline •H W # 7 d u e •M i d t e r m Average:83.8 Median:91.0 Std Dev:17.02 Topics: – Memory hierarchy – FPGAs – Verilog Basics – Behavioral Synthesis

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2 3 Sources: TSR, Katz, Boriello, Vahid, Perkowski CSE140: Components and Design Techniques for Digital Systems Verilog Tajana Simunic Rosing 4 Sources: TSR, Katz, Boriello, Vahid, Perkowski Verilog • Supports structural and behavioral descriptions • Structural – explicit structure of the circuit – e.g., each logic gate instantiated and connected to others • Behavioral – program describes input/output behavior of circuit – many structural implementations could have same behavior – e.g., different implementation of one Boolean function
3 5 Sources: TSR, Katz, Boriello, Vahid, Perkowski module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2; inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2); endmodule Structural model 6 Sources: TSR, Katz, Boriello, Vahid, Perkowski module xor_gate (out, a, b); input a, b; output out; reg out; assign #6 out = a ^ b; endmodule Simple behavioral model • Continuous assignment

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4 7 Sources: TSR, Katz, Boriello, Vahid, Perkowski module xor_gate (out, a, b); input a, b; output out; reg out; always @(a or b) begin #6 out = a ^ b; end endmodule Simple behavioral model • always block 8 Sources: TSR, Katz, Boriello, Vahid, Perkowski module testbench (x, y); output x, y; reg [1:0] cnt; initial begin cnt = 0; repeat (4) begin #10 cnt = cnt + 1; \$display ("@ time=%d, x=%b, y=%b, cnt=%b", \$time, x, y, cnt); end #10 \$finish; end assign x = cnt[1]; assign y = cnt[0]; endmodule Driving a simulation through a “testbench”
5 9 Sources: TSR, Katz, Boriello, Vahid, Perkowski Complete simulation • Instantiate stimulus component and device to test a b z test-bench x y 10 Sources: TSR, Katz, Boriello, Vahid, Perkowski module Compare1 (Equal, Alarger, Blarger, A, B); input A, B; output Equal, Alarger, Blarger; assign #5 Equal = (A & B) | (~A & ~B); assign #3 Alarger = (A & ~B); assign #3 Blarger = (~A & B); endmodule Comparator example

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6 11 Sources: TSR, Katz, Boriello, Vahid, Perkowski module life (n0, n1, n2, n3, n4, n5, n6, n7, self, out); input n0, n1, n2, n3, n4, n5, n6, n7, self; output out; reg out; reg [7:0] neighbors; reg [3:0] count;
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## This note was uploaded on 02/14/2008 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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lect13 verilog and basics - CSE140: Components and Design...

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