This preview shows pages 1–8. Sign up to view the full content.
11Sources: TSR, Katz, Boriello, Vahid, PerkowskiCSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing2Sources: TSR, Katz, Boriello, Vahid, PerkowskiAnnoncements and Outline•HW#9 due Thursday, 11/30, at the beginning of the class•Pick up graded homework at my assistant’s office, check webct grades •Final exam – Tuesday, December 5th, at 11:30am–Everything covered in lectures, whole book & all handouts– Format: •Problems similar to HW and previous exams•Multiple choice and/or T/F questions on the assigned reading•Register Transfer Level design (RTL)– Definition– Methodology– Examples•Simple CPU design
has intentionally blurred sections.
Sign up to view the full version.