lect14 RTL design - CSE140 Components and Design Techniques...

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1 1 Sources: TSR, Katz, Boriello, Vahid, Perkowski CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing 2 Sources: TSR, Katz, Boriello, Vahid, Perkowski Annoncements and Outline HW#9 due Thursday, 11/30, at the beginning of the class Pick up graded homework at my assistant’s office, check webct grades Final exam – Tuesday, December 5 th , at 11:30am Everything covered in lectures, whole book & all handouts – Format: Problems similar to HW and previous exams Multiple choice and/or T/F questions on the assigned reading Register Transfer Level design (RTL) – Definition – Methodology – Examples Simple CPU design
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