lect14 RTL design

lect14 RTL design - CSE140: Components and Design...

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1 1 Sources: TSR, Katz, Boriello, Vahid, Perkowski CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing 2 Sources: TSR, Katz, Boriello, Vahid, Perkowski Annoncements and Outline HW#9 due Thursday, 11/30, at the beginning of the class Pick up graded homework at my assistant’s office, check webct grades Final exam – Tuesday, December 5 th , at 11:30am – Everything covered in lectures, whole book & all handouts – Format: • Problems similar to HW and previous exams • Multiple choice and/or T/F questions on the assigned reading Register Transfer Level design (RTL) – Definition – Methodology –E x am p l e s Simple CPU design
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2 3 Sources: TSR, Katz, Boriello, Vahid, Perkowski CSE140: Components and Design Techniques for Digital Systems RTL Design Process Tajana Simunic Rosing 4 Sources: TSR, Katz, Boriello, Vahid, Perkowski RTL Design Method 5.2
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3 5 Sources: TSR, Katz, Boriello, Vahid, Perkowski RTL for Datapath & Control 6 Sources: TSR, Katz, Boriello, Vahid, Perkowski RTL Design Method Example • Soda dispenser c : bit input, 1 when coin deposited a : 8-bit input having value of deposited coin s : 8-bit input having cost of a soda d : bit output, processor sets to 1 when total value of deposited coins equals or exceeds cost of a soda a s c d Soda dispenser processor 25 1 0 25 1 1 50 0 0 0 0 tot: tot: 50
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4 7 Sources: TSR, Katz, Boriello, Vahid, Perkowski Step 1: Capture High-Level State Machine 88 a s c d Soda dispenser processor 8 Sources: TSR, Katz, Boriello, Vahid, Perkowski Step 2: Create Datapath Inputs : c (bit), a(8 bits), s (8 bits) Outputs : d (bit) Local registers: tot (8 bits) Wait Add Disp Init d=0 tot=0 c (t ot<s) c (tot<s) d=1 c tot= tot+a
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5 9 Sources: TSR, Katz, Boriello, Vahid, Perkowski Step 3: Connect Datapath to a Controller tot_lt_s tot_clr tot_ld Controller Datapath s c d a 88 ld clr tot 8-bit < 8-bit adder 8 8 8 8 sa Datapath tot_ld tot_clr tot_lt_s 10 Sources: TSR, Katz, Boriello, Vahid, Perkowski Step 4 – Derive the Controller’s FSM tot_lt_s tot_clr tot_ld Controller s c d a ld clr tpt 8-bit < 8-bit adder 8 8 8 8 Datapath tot_ld tot_clr tot_lt_s
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6 11 Sources: TSR, Katz, Boriello, Vahid, Perkowski Completing the Design • Implement the FSM as a state register and logic d 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 n0 1 1 1 1 1 1 0 0 1 0 n1 0 0 0 0 1 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 c 0 0 1 1 0 0 1 1 0 0 s1 0 0 0 0 0 0 0 0 1 1 s0 0 0 0 0 1 1 1 1 0 1 tot_lt_s tot_ld tot_clr Init Wait Add Disp Inputs:c, tot_lt_s (bit) Outputs:d, tot_ld , tot_clr (bit) Wa i t Disp Init d=0 tot_clr=1 c ’* to t_ lt_ s c’ * tot_lt_s d=1 c tot_ld=1 c d tot_ld tot_clr tot_lt_s Controller Add 12 Sources: TSR, Katz, Boriello, Vahid, Perkowski RTL Design example: Laser-Based Distance Measurer • Laser-based distance measurement – pulse laser, measure time T to sense reflection – Laser light travels at speed of light, 3*10 8 m/sec – Distance is thus D = T sec * 3*10 8 m/sec / 2 Object of interest D 2D = T sec * 3*10 8 m/sec sensor laser T (in seconds)
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7 13 Sources: TSR, Katz, Boriello, Vahid, Perkowski Laser-Based Distance Measurer – I/O Definition
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This note was uploaded on 02/14/2008 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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lect14 RTL design - CSE140: Components and Design...

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