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lect15 simple processor design

lect15 simple processor design - CSE140 Components and...

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1 1 Sources: TSR, Cummings, KFR CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing 2 Sources: TSR, Cummings, KFR Announcements and Outline HW#9 due Thursday, 11/30, at the beginning of the class Check webct grades, make sure everything is there and is correct Pick up graded homework at my assistant’s office Final exam – Tuesday, December 5 th , at 11:30am in CENTR 113 Everything covered in lectures, whole book & all handouts – Format: Problems similar to HW and previous exams Multiple choice and/or T/F questions on the assigned reading Discussion session will go over the previous year’s final Simple CPU design Questions?
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2 3 Sources: TSR, Cummings, KFR CSE140: Components and Design Techniques for Digital Systems Single Cycle CPU Design Tajana Simunic Rosing 4 Sources: TSR, Cummings, KFR INSTRUCTION MEMORY READ ADDRESS INSTRUCTION [31-0] MUX 0 1 MUX 0 1 ALU ZERO RESULT DATA MEMORY ADDRESS WRITE DATA READ DATA MUX 0 1 ADDER RESULT ADDER RESULT PC MUX 0 1 4 Sign Extend ALU CONTROL INSTRUCTION[15-0] INSTRUCTION[5-0] << 2 CON TROL INSTRUCTION[31-26] INSTRUCTION[25-21] INSTRUCTION[20-16] INST[15-11] BRANCH REG_DST REG_WRITE ALU_SRC ALU_OP MEM_READ,MEM_WRITE MEM_TO_REG MIPS Single-Cycle Datapath & Control REGISTERS READ REGISTER 1 READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2
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