lect15 simple processor design

Lect15 simple - CSE140 Components and Design Techniques for Digital Systems Tajana Simunic Rosing 1 Sources TSR Cummings KFR Announcements and

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1 1 Sources: TSR, Cummings, KFR CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing 2 Sources: TSR, Cummings, KFR Announcements and Outline HW#9 due Thursday, 11/30, at the beginning of the class Check webct grades, make sure everything is there and is correct Pick up graded homework at my assistant’s office Final exam – Tuesday, December 5 th , at 11:30am in CENTR 113 – Everything covered in lectures, whole book & all handouts – Format: • Problems similar to HW and previous exams • Multiple choice and/or T/F questions on the assigned reading – Discussion session will go over the previous year’s final Simple CPU design •Q u e s t i o n s ?
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2 3 Sources: TSR, Cummings, KFR CSE140: Components and Design Techniques for Digital Systems Single Cycle CPU Design Tajana Simunic Rosing 4 Sources: TSR, Cummings, KFR INSTRUCTION MEMORY READ ADDRESS INSTRUCTION [31-0] MUX 0 1 MUX 0 1 ALU ZERO RESULT DATA MEMORY ADDRESS WRITE DATA READ DATA MUX 01 ADDER RESULT ADDER RESULT PC MUX 0 1 4 Sign Extend ALU CONTROL INSTRUCTION[15-0] INSTRUCTION[5-0] << 2 CON TROL INSTRUCTION[31-26] INSTRUCTION[25-21] INSTRUCTION[20-16] INST[15-11] BRANCH REG_DST REG_WRITE ALU_SRC ALU_OP MEM_READ,MEM_WRITE MEM_TO_REG MIPS Single-Cycle Datapath & Control REGISTERS READ REGISTER 1 READ REGISTER 2 WRITE REGISTER WRITE DATA READ DATA 1 READ DATA 2
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3 5 Sources: TSR, Cummings, KFR CPU Components • Combinational logic: – Boolean equations, logic gates – Multiplexors and decoders – ALU: executes arithmetic /logical operations 6 Sources: TSR, Cummings, KFR M U X 2-input, 32-bit MUX I0 I1 S O 32 32 32 S I0 31 I1 31 I0 30 I1 30 I0 0 I1 0 O 31 O 30 O 0 0 1 M U X M U X M U X implementation 0 1 0 1 0 1 • Selects one input as the output
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4 7 Sources: TSR, Cummings, KFR Decoder 2 input, 2 2 = 4 outputs 2-to-4 DECODER I0 I1 O0 O1 O2 O3 I0 I1 O0 O1 O2 O3 0 0 0 1 1 1 1 0 0 O2 0 0 0 O3 0 1 0 O1 0 0 1 0 1 0 1 0 0 O0 I0 I1 ¬ ¬ ¬ ¬ implementation Translates input into binary number B and turns on output B 8 Sources: TSR, Cummings, KFR Full 32-bit ALU 32-bit ALU A B CarryIn OP CODE Result Overflow CarryOut 32 32 32 Performs: AND, OR, NOT, ADD, SUB, Overflow Detection, GTE
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5 9 Sources: TSR, Cummings, KFR 0 1 xor MSB ALU ¬ + A31 B31 result 0 1 2 OP 3 ADD CarryOut ¬ Binvert CarryIn overflow 4 GTEin = 0 xor ¬ GTEout If GTEout = 1, A B 10 Sources: TSR, Cummings, KFR ALU Design Example 1 1 1 1 A and B 0 1 1 A or B 1 0 1 A xor B 0 0 1 A+B 1 1 0 A-B 0 1 0 B-A 1 0 0 0 0 0 0 Function S0 S1 S2
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6 11 Sources: TSR, Cummings, KFR CPU Components • Combinational logic: – Boolean equations, logic gates – Multiplexors and decoders – ALU: executes arithmetic /logical operations • Sequential logic: – The clock – Storage (memory) elements – Counters 12 Sources: TSR, Cummings, KFR Determining Clock Frequency • Frequency limited by longest register-to-register delay – Known as critical path – If clock is any faster, incorrect data may be stored into register – Longest path on right is 2 ns • Ignoring wire delays, and register setup and hold times, skew 5.4 a + b c 2 ns delay clk
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7 13
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This note was uploaded on 02/14/2008 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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Lect15 simple - CSE140 Components and Design Techniques for Digital Systems Tajana Simunic Rosing 1 Sources TSR Cummings KFR Announcements and

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