RTL handout

RTL handout - C-based Interactive RTL Design Methodology...

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Unformatted text preview: C-based Interactive RTL Design Methodology Dongwan Shin, Andreas Gerstlauer, Rainer Domer and Daniel Gajski Technical Report CECS-03-42 December 1, 2003 Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697-3425, USA (949) 824-8059 { dongwans, gerstl, doemer, gajski } @cecs.uci.edu 1 C-based Interactive RTL Design Methodology Dongwan Shin, Andreas Gerstlauer, Rainer Domer and Daniel Gajski Technical Report CECS-03-42 December 1, 2003 Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697-3425, USA (949) 824-8059 { dongwans, gerstl, doemer, gajski } @cecs.uci.edu Abstract Much effort in RTL design has been devoted to developing push-button types of tools. However, given the highly com- plex nature of RTL design, interactive design space exploration with assistance of tools and algorithms can be more effective. In this report, we propose an interactive RTL design environment, targeting a generic RTL processor architecture includ- ing pipelining, multicycling and chaining. Tasks in the RTL design process include clock definition, component allocation, scheduling, binding, and validation. In our interactive design environment, the user can control the design process at every stage, observe the effects of design decisions, and manually override synthesis decisions at will. We also provide a simul- taneous scheduling and binding algorithm to automate RTL synthesis process. In the end, we present a set of experimental results that demonstrates the benefits of the proposed approach. 2 Contents 1. Introduction 1 2. Related Work 2 3. RTL Design Environment 2 3.1. System Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.2. RTL Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.3. Preprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.4. Finite State Machine with Data (FSMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.5. Input Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.6. RTL Component Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.7. Synthesis Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.7.1 GUI for Interactive Decision-making . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.8. Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.9. Target Processor Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Interactive RTL Synthesis Example 7 4.1. Synthesis Decisions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .....
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RTL handout - C-based Interactive RTL Design Methodology...

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