lect5-Two and Multilevel logic implementation

# lect5-Two and Multilevel logic implementation - CSE140...

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1 1 Sources: TSR, Katz, Boriello & Vahid CSE140: Components and Design Techniques for Digital Systems Two and Multilevel logic implementation Tajana Simunic Rosing 2 Sources: TSR, Katz, Boriello & Vahid Two-level logic using NAND gates • Replace minterm AND gates with NAND gates • Place compensating inversion at inputs of OR gate • OR gate with inverted inputs is a NAND gate – de Morgan’s: A’ + B’ = (A • B)’ • Two-level NAND-NAND network – inverted inputs are not counted – in a typical circuit, inversion is done once and signal distributed

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2 3 Sources: TSR, Katz, Boriello & Vahid Two-level logic using NAND and NOR gates • NAND-NAND and NOR-NOR networks – de Morgan’s law: (A + B)’ = A’ • B’ (A • B)’ = A’ + B’ – written differently: A + B = (A’ • B’)’ (A • B) = (A’ + B’)’ 4 Sources: TSR, Katz, Boriello & Vahid A B C D Z Conversion between forms • Introduce "bubbles“ - inversions – conservation of inversions – do not alter logic function
3 5 Sources: TSR, Katz, Boriello & Vahid Conversion between forms • Example: map AND/OR network to NOR/NOR network A B C D Z 6 Sources: TSR, Katz, Boriello & Vahid Multiple-Output Circuits • Many circuits have more than one output • Can give each a separate circuit, or can share gates • Ex: F = ab + c’, G = ab + bc Option 1: Separate circuits Option 2: Shared gates

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4 7 Sources: TSR, Katz, Boriello & Vahid Multiple-Output Example: BCD to 7-Segment Converter a = w’x’y’z’ + w’x’yz’ + w’x’yz + w’xy’z + w’xyz’ + w’xyz + wx’y’z’ + wx’y’z abcdefg = 1111110 0110000 1101101 a f b d g e c (b) (a) b = w’x’y’z’ + w’x’y’z + w’x’yz’ + w’x’yz + w’xy’z’ + w’xyz + wx’y’z’ + wx’y’z 8 Sources: TSR, Katz, Boriello & Vahid Multi-level logic x = A D F + A E F + B D F + B E F + C D F + C E F + G – reduced sum-of-products form – already simplified – 6 x 3-input AND gates + 1 x 7-input OR gate – 25 wires (19 literals plus 6 internal wires)
5 9 Sources: TSR, Katz, Boriello & Vahid Non-Ideal Gate Behavior – Delay • Real gates don’t respond immediately to input changes – Rise/fall time – Delay – Pulse width aF Time F a 10 Sources: TSR, Katz, Boriello & Vahid F is not always 0 pulse 3 gate-delays wide D remains high for three gate delays after A changes from low to high F AB C D Momentary changes in outputs • Can be useful — pulse shaping circuits • Can be a problem — incorrect circuit operation (glitches/hazards) • Example: pulse shaping circuit –A ’•A = 0 – delays matter

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6 11 Sources: TSR, Katz, Boriello & Vahid Hazards • Glitch – unwanted pulse on the output • Circuit with a potential for a glitch has a hazard • Three types: – Static-0 : output should be 0 but has a 1 glitch
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lect5-Two and Multilevel logic implementation - CSE140...

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