F03Exam3

# F03Exam3 - i G s-a-1 ii J s-a-1 iii A s-a-0 4 Find a set of minimum number of flip-flops that should be scanned so that the circuit below becomes a

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55:138 Testing Digital Logic Circuits S.M. Reddy 12/02/03 Exam III Fall 2003 1. Determine all AND and OR bridging faults detected by 1010 on the circuit below.

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2. Derive a minimum pseudoexhaustive test set for circuit below with the dotted lines representing the partitions.
3. Assume all 8 inputs are applied to the circuit below. Determine the counts and also determine if any of the faults alias if: a) Transition counting is used as signature b) Parity-check compression is used c) Ones-counting is used as signature for the following faults:

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Unformatted text preview: ( i ) G s-a-1 ( ii ) J s-a-1 ( iii) A s-a-0 4) Find a set of minimum number of flip-flops that should be scanned so that the circuit below becomes a balanced pipeline. 5) Consider the scan design shown below. For the case listed below, determine the best way, among together and overlap mode, to organize the testing of the blocks C1, C2, & C3 to minimize the test time. Explain your reasoning. Assume C1 requires 6 test vectors, C2 requires 10 test vectors, and C3 requires 2 test vectors....
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## This test prep was uploaded on 04/22/2008 for the course EE 1 taught by Professor Dsd during the Fall '03 term at University of Iowa.

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F03Exam3 - i G s-a-1 ii J s-a-1 iii A s-a-0 4 Find a set of minimum number of flip-flops that should be scanned so that the circuit below becomes a

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