hw4sol

# hw4sol - Solutions Homework 4 I (a) PLA Implementation: (b)...

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Solutions – Homework 4 I (a) PLA Implementation:

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(b) PAL Implementation 4.7(b) Output must be (P+Q) when S is 1. If S is 0, output should be (R+T).
4.19(d) Decoder 5.5(a) Subtractor problem Truth table for the required binary subtractor is: A B B I D B L 0 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1

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D = (A’)(B’)(B I ) + (A’)B(B I ) + A(B’)(B I )’ + ABB I Or simply: D = A xor B xor C B L = (A’)B + (A’)B I + BB I (b) A 4-bit subtractor could be implemented by cascading four 1-bit subtractors. III (a) Ripple carry adder Delay through a 1-bit full adder = 2. Delay through a 4-bit ripple carry adder = 2*4 = 8. Note: Carry out from the last bit is available after 8 gate delays, whereas Sum is available after 7 gate delays. (b) Carry lookahead adder: Time for calculating all the propagate signals(P i ) = 1 gate delay Time for calculating all the generate signals(G i ) = 1 gate delay. BL
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## hw4sol - Solutions Homework 4 I (a) PLA Implementation: (b)...

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