lect6 mux demux

lect6 mux demux - CSE140: Components and Design Techniques...

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1 1 Sources: TSR, Katz, Boriello & Vahid CSE140: Components and Design Techniques for Digital Systems Tajana Simunic Rosing 2 Sources: TSR, Katz, Boriello & Vahid Overview • Midterm #1 – Tuesday, 10/17 11am – Appendix A,B, Chap. 1-5; – Everything covered in class – Closed book and notes – OK to bring one 8 1/2 x 11” sheet with handwritten notes • Homework – HW#3 due Thursday, 10/12 – Will be due on Tuesdays starting after Midterm #1 • Today and next time: – Regular logic implementation – Mux and demux – Design examples to illustrate application of combinational logic – Sequential circuits!
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2 3 Sources: TSR, Katz, Boriello & Vahid CSE140: Components and Design Techniques for Digital Systems Regular logic implementation Tajana Simunic Rosing 4 Sources: TSR, Katz, Boriello & Vahid ••• inputs AND array outputs OR array product terms Programmable logic arrays • Pre-fabricated building block of many AND/OR gates – "personalized" by making/breaking connections among the gates – programmable array block diagram for sum of products form
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3 5 Sources: TSR, Katz, Boriello & Vahid ABC F1 F2 F3 F0 AB B'C AC' B'C' A Before & after programming • Two different technologies: – fuse (normally connected, break unwanted ones) – anti-fuse (normally disconnected, make wanted connections) Before After 6 Sources: TSR, Katz, Boriello & Vahid A B C F1F2F3F4F5F6 0000 0 1 1 0 0 0010 1 0 1 1 1 0100 1 0 1 1 1 0110 1 0 1 0 0 1000 1 0 1 1 1 1010 1 0 1 0 0 1100 1 0 1 0 0 1111 1 0 0 1 1 A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC F1 F2 F3 F4 F5 F6 full decoder as for memory address bits stored in memory Programmable logic array example • Multiple functions of A, B, C – F1 = A B C – F2 = A + B + C – F3 = A' B' C' – F4 = A' + B' + C' – F5 = A xor B xor C – F6 = A xnor B xnor C
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4 7 Sources: TSR, Katz, Boriello & Vahid a given column of the OR array has access to only a subset of the possible product terms PALs and PLAs • Programmable logic array (PLA) – what we've seen so far – unconstrained fully-general AND and OR arrays • Programmable array logic (PAL) – constrained topology of the OR array – innovation by Monolithic Memories – faster and smaller OR plane 8 Sources: TSR, Katz, Boriello & Vahid Example • Map the following functions to the PLA below: – W = AB + A’C’ + BC’ – X = ABC + AB’ + A’B – Y = ABC’ + BC + B’C’ ABC WXY
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5 9 Sources: TSR, Katz, Boriello & Vahid decoder 0n - 1 Address 2 -1 n 0 1 1 1 1 word[i] = 0011 word[j] = 1010 bit lines (normally 1; set to 0 by a switch) j i internal organization word lines Read-only memories • Two dimensional array of 1s and 0s – entry (row) is called a "word" – width of row = word-size – index is called an "address" – address is input – selected word is output 10
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This note was uploaded on 02/14/2008 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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lect6 mux demux - CSE140: Components and Design Techniques...

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