hw4 - 4.7 (b) 4.19 (d) 5.5 (a), (b) (Note: For part (b),...

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CSE 140 Homework # 4 Due date: Tuesday, 10/24/2006 You must show ALL steps for obtaining the solution. Just reporting the correct answer, without showing work performed at each step will result in getting 0 points for that problem. Text book: Contemporary Logic Design (2nd Edition) I Consider the following functions D BC C AB BD A D C B A G ACD D AC BD A D B A D C B A F ' ' ' ' ) , , , ( ' ' ' ' ' ' ) , , , ( + + = + + + = Implement F and G using 1. A PLA 2. A PAL, with two 4-input OR gates. (updated: 10/19) II. Textbook Problems:
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Unformatted text preview: 4.7 (b) 4.19 (d) 5.5 (a), (b) (Note: For part (b), show how you would implement a 4-bit subtractor) III. What are the critical delays (in terms of gate-delays) through each of the following circuits? a) A 4-bit ripple carry adder implemented using four full adders b) A 4-bit carry lookahead adder IV 6.1, 6.9, from text book 6.10, from textbook (use the following timing diagram instead of the one given in textbook)...
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This homework help was uploaded on 02/14/2008 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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