hw5sol

hw5sol - Homework 5 Solutions 6.13 1 Draw the truth table...

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Homework 5 - Solutions Page 1 of 12 6.13 1) Draw the truth table for output (Q + ) in terms of input J and K. 2) Since we are using a D flip-flop, use the excitation table to find the value of D for each input combination. 3) Find the logic equation for D in terms of inputs J, K and the present state Q. 4) Implement the logic to get a JK flip-flop using a D flip-flop. 6.16
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Homework 5 - Solutions Page 2 of 12 6.17 T Q D Thus T Q Q = = + , 6.19 T Q Q + D 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 Q Q + D 0 0 0 0 1 1 1 0 0 1 1 1 Excitation table for D flip- flop
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Homework 5 - Solutions Page 3 of 12 6.21 Placing two synchronizers in series helps reduce the probability of synchronizer failure because it is in effect providing the system two clock periods to stabilize instead of one. This effect is very similar to increasing the clock period of the receiver so that it has more time to decide. Even though it seems logical to put more synchronizers in series to even further reduce the probability of synchronizer failure, this approach has the severe penalty in that each synchronizer adds another full clock period before the input can be used.
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Homework 5 - Solutions Page 4 of 12 II Show how to implement a J-K flip-flop starting with a T flip-flop.
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This homework help was uploaded on 02/14/2008 for the course CSE 140 taught by Professor Rosing during the Fall '06 term at UCSD.

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hw5sol - Homework 5 Solutions 6.13 1 Draw the truth table...

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