lect 5 cpu organization -exceptions

lect 5 cpu organization -exceptions - CSE 141 Dean Tullsen...

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Unformatted text preview: CSE 141 Dean Tullsen Historical Context: Simplifying Control Design Through Microprogramming CSE 141 Dean Tullsen The Problem with FSMs as control sequencers • They get unmanageable quickly as they grow. – hard to specify – hard to manipulate – error prone – hard to visualize CSE 141 Dean Tullsen Implementing a control FSM Opcode State Reg Inputs O u t p u t s Control Logic CSE 141 Dean Tullsen Implementing a control FSM with ROM Opcode State Reg Address O u t p u t s ROM Each line in the ROM contains control signal outputs (an operation), and next-state outputs (branch destination) CSE 141 Dean Tullsen Implementing a control FSM with ??? Opcode Next address calc Address O u t p u t s ROM CSE 141 Dean Tullsen Implementing a control FSM with a microprogram Opcode μ PC + next μ PC logic Address O u t p u t s μ program in ROM Each line in the ROM is now a microprogram instruction, corresponding to a FSM state, with an operation (control signals) and branch destination (next state info). CSE 141 Dean Tullsen Microprogram Implementation Microprogram counter Address select logic Adder 1 Input Datapath& control& outputs Microcode& storage Inputs from instruction& register opcode field Outputs Sequencing& control CSE 141 Dean Tullsen Microprogramming • Being able to specify sequences of signals doesn’t necessarily make it “easy”. • Groups of signals are combined and given symbolic names. E.g., – MemRead, ALUSrcA = 0, IorD = 0, ALUSrcB = 01… = “fetch” – RegDst=1, MemtoReg=0, regwrite=1 => “rd = ALUout” – RegDst=0, MemtoReg=1, regwrite=1 => “rt = MDR” • So a microprogram might be: start: fetch decode; goto “opcode” … add: src1=A; src2=B; add rd=ALUout; goto start CSE 141 Dean Tullsen...
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lect 5 cpu organization -exceptions - CSE 141 Dean Tullsen...

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