lect 5 cpu organization -multicycle

lect 5 cpu organization -multicycle - Why a Multiple Clock...

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CSE 141 Dean Tullsen Multiple Clock Cycle CPU or Breaking Up Is Hard To Do CSE 141 Dean Tullsen Why a Multiple Clock Cycle CPU? the problem => single-cycle cpu has a cycle time long enough to complete the longest instruction in the machine the solution => break up execution into smaller tasks, each task taking a cycle, different instructions requiring different numbers of cycles or tasks other advantages => reuse of functional units (e.g., alu, memory) ET = IC * CPI * CT CSE 141 Dean Tullsen Breaking Execution Into Clock Cycles We will have five execution steps (not all instructions use all five) & register fetch access We will use Register-Transfer-Language (RTL) to describe these steps CSE 141 Dean Tullsen Breaking Execution Into Clock Cycles Introduces extra registers when: – signal is in one clock cycle and used in another, AND – the inputs to the functional block that outputs this signal can __________ before the signal is written into a state element. Significantly complicates control. Why? The goal is to balance the amount of work done each cycle.
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CSE 141 Dean Tullsen Multicycle datapath Shift& left 2 PC Memory & MemData Write& data M& u& x 0 1 Registers Write& register Write& data Read& data 1 Read& data 2 Read& register 1 Read& register 2 M& u& x 0 1 M& u& x 0 1 4 Instruction& [15–0] Sign& extend 32 16 Instruction& [25–21] Instruction& [20–16] Instruction& [15–0] Instruction& register 1 M& u& x 0 3 2 M& u& x ALU& result ALU Zero Memory& data& register Instruction& [15–11] A B ALUOut 0 1 Address CSE 141 Dean Tullsen 1. Fetch IR = Mem[PC] PC = PC + 4 ( may not be final value of PC ) CSE 141 Dean Tullsen 2. Instruction Decode and Register Fetch compute target before we know if it will be used (may not be branch, branch may not be taken) is a new state element (temp register) everything up to this point must be Instruction- independent , because we still haven’t the instruction. everything instruction (opcode)-dependent from here on. A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUOut = PC + (sign-extend (IR[15-0]) << 2) CSE 141 Dean Tullsen 3. Execution, memory address computation, or branch completion Memory reference (load or store) ALUOut = A + sign-extend(IR[15-0]) R-type ALUout = A op B Branch if (A == B) PC = ALUOut At this point, Branch is complete, and we start over; others require more cycles.
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CSE 141 Dean Tullsen 4. Memory access or R-type completion Memory reference –l o a d MDR = Mem[ALUout] –s t o r e Mem[ALUout] = B R-type Reg[IR[15-11]] = ALUout R-type is complete CSE 141 Dean Tullsen 5. Memory Write-Back Reg[IR[20-16]] = MDR memory instruction is complete CSE 141 Dean Tullsen Summary of execution steps Step R-type Memory Branch Instruction Fetch IR = Mem[PC] PC = PC + 4 Instruction Decode/ register fetch A = Reg[IR[25-21]] B = Reg[IR[20-16]] ALUout = PC + (sign-extend(IR[15-0]) << 2) Execution, address computation, branch completion ALUout = A op B ALUout = A + sign- extend(IR[15-0]) if (A==B) then PC=ALUout Memory access or R- type completion Reg[IR[15-11]] = ALUout memory-data = Mem[ALUout] or Mem[ALUout]= B Write-back Reg[IR[20-16]] = memory-data 1. Instruction Fetch IR = Memory[PC] PC = PC + 4 Shift& left 2
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This note was uploaded on 02/14/2008 for the course CSE 141 taught by Professor Tullsen during the Fall '06 term at UCSD.

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lect 5 cpu organization -multicycle - Why a Multiple Clock...

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