lect7 virtual memory

lect7 virtual memory - Advanced Cache Architectures Hiding...

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CSE 141 Dean Tullsen Advanced Cache Architectures and Virtual Memory CSE 141 Dean Tullsen Advanced Cache Architectures Hiding cache miss latencies Non-blocking caches – do not stall, or stop accessing cache, on a miss. DM hit time + set-associative hit rate Victim caches High instruction fetch bandwidth Trace caches CSE 141 Dean Tullsen Victim Cache cache memory Victim Cache CSE 141 Dean Tullsen Trace Cache Conventional Cache Trace Cache A B C beq J: D E F J: G H jsr W W X ret A B C beq D E F G Hj s r I J K L M N W X ret
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CSE 141 Dean Tullsen Other Cache Accelerators Software transformations (e.g., tiling ) which change memory access order to increase locality. Software Cache Prefetching – bring data into the cache before the code executes the load. – Prefetch(A) – Helper thread prefetching Hardware Cache Prefetching – Next-line prefetcher – on a cache miss, or first access to a prefetched line, prefetch next line. – Stream buffers – detects address stride, and keeps a fifo full of next n (e.g., 4) accesses. CSE 141
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This note was uploaded on 02/14/2008 for the course CSE 141 taught by Professor Tullsen during the Fall '06 term at UCSD.

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lect7 virtual memory - Advanced Cache Architectures Hiding...

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